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rocket-tools/riscv-tests.git
attempt-travis-fix
ceasetest2
compliance_tests
cs152-sp18-lab3
debug
debug-0.13
debug-clear-satp
debug-delete-sim
debug_auth
debug_disassemble
disable_unavailable
dma-memcpy
eos20-bringup
hw_watchpoint
interrupts
master
misc
no_progbuf
priv
privchange-dontdeleteme
python3
rekall
resume_from_trigger
riscv-tests-sail
rtos
rvt-master
smi-demo
split-isa-tests
sqrt-171
tmp
trap_entry_align
trap_entry_align-1
travis-dev
trigger_priority
usb_error
xlen_fix
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Files
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2022-10-07
debug: On failure, disassemble close instructions.
debug_disassemble
Tim Newsome
1
-1
/
+1
2022-10-06
Merge pull request #414 from YenHaoChen/pr-timestamp
Tim Newsome
1
-2
/
+2
2022-10-05
Update testlib.py; remove ANSI escape sequences
YenHaoChen
1
-1
/
+2
2022-10-05
update gdbserver.py; release tolerance value of MemorySampleTest()
YenHaoChen
1
-2
/
+2
2022-09-27
rv64ui test misaligned load/store data (#410)
John Ingalls
2
-0
/
+388
2022-09-27
zicboz: comment # (#412)
John Ingalls
1
-1
/
+1
2022-09-26
zicbo test zero (#411)
John Ingalls
3
-2
/
+49
2022-07-25
Ignore `mip` and `time` in DisconnectTest. (#406)
Tim Newsome
1
-1
/
+2
2022-07-22
Fix string formatting in testlib.assertTrue()
Tim Newsome
1
-1
/
+1
2022-07-14
Pylint fix. (#405)
Tim Newsome
1
-1
/
+2
2022-07-14
Only run SemihostingFileio on single hart systems. (#404)
Tim Newsome
1
-0
/
+11
2022-07-11
Debug MemorySampleMixed: Disable 64-bit sampling on 32-bit targets (#402)
Luke Wren
1
-2
/
+6
2022-07-08
Fix SemihostingFileio (#403)
Tim Newsome
1
-1
/
+2
2022-07-01
Complete this pass of pylint changes. (#401)
Tim Newsome
2
-149
/
+151
2022-06-23
Another pylint upgrade. (#398)
Tim Newsome
3
-173
/
+191
2022-06-21
Update information about Makefile fragments (#399)
Mehmet Oguz Derin
1
-4
/
+2
2022-06-09
Test misaligned stores. (#397)
Tim Newsome
8
-0
/
+158
2022-06-08
Merge pull request #395 from riscv-software-src/misaligned_store
Andrew Waterman
10
-6
/
+164
2022-06-08
Test semihosting_fileio
Tim Newsome
2
-4
/
+27
2022-06-07
Test misaligned loads.
Tim Newsome
8
-0
/
+160
2022-06-07
Set TESTNUM before executing code.
Tim Newsome
3
-6
/
+4
2022-06-06
Revert unaligned tests.
Tim Newsome
3
-51
/
+1
2022-06-06
Test unaligned ld accesses.
Tim Newsome
1
-0
/
+27
2022-06-06
Add unaligned test cases for lw
Tim Newsome
1
-0
/
+23
2022-06-06
Set TESTNUM before executing code.
Tim Newsome
1
-1
/
+1
2022-05-31
Address pylint warnings. (#385)
Tim Newsome
8
-15
/
+16
2022-05-31
Fix GdbTest.disable_pmp failing on systems which support NAPOT but not TOR re...
Luke Wren
1
-2
/
+8
2022-05-28
Permit mtval to be zero in misaligned address test, fixes #389 (#390)
Luke Wren
1
-0
/
+2
2022-05-16
V implies FD now. (#382)
Tim Newsome
1
-3
/
+3
2022-04-25
Add EbreakTest. (#380)
Tim Newsome
2
-0
/
+62
2022-04-07
Make download test data const. (#378)
Tim Newsome
1
-2
/
+2
2022-03-08
Add Zfh and Svnapot to Spike ISA string
Andrew Waterman
1
-2
/
+2
2022-03-03
With new OpenOCD, gdb prints thread info differently (#373)
Tim Newsome
1
-1
/
+2
2022-03-03
Add assert to MemorySampleTest. (#370)
Tim Newsome
1
-0
/
+1
2022-02-09
Debug test to check that stepping doesn't inappropriately switch to Thread 1 ...
Greg Savin
1
-0
/
+21
2022-01-06
Add gdb.interact() for debug tests. (#367)
Tim Newsome
1
-0
/
+18
2021-11-29
Fix TranslateTests. (#365)
Tim Newsome
2
-5
/
+7
2021-11-12
Set `riscv resume_order reversed`. (#363)
Tim Newsome
1
-0
/
+2
2021-11-12
Create DisconnectTest. (#364)
Tim Newsome
2
-32
/
+53
2021-11-12
Add timing output to DebugTurboStep. (#362)
Tim Newsome
1
-1
/
+5
2021-10-05
Remove slen. (#360)
Tim Newsome
4
-22
/
+16
2021-07-22
Fix #352 (#353)
Daniel Lustig
1
-2
/
+2
2021-07-21
Move the Svnapot test to its own folder (#351)
Daniel Lustig
4
-1
/
+10
2021-07-19
Bump env
Andrew Waterman
1
-20
/
+0
2021-07-19
Add a test for Svnapot (#349)
Daniel Lustig
2
-0
/
+173
2021-07-19
Debug tests: catch write to nonexistent trigger registers in entry.S (#348)
Luke Wren
1
-0
/
+7
2021-06-29
Update README.md (#342)
mymatin
1
-1
/
+1
2021-06-08
Tweaks for multispike. (#339)
Tim Newsome
3
-9
/
+19
2021-06-01
Enable access to cycle counter before trying to write it
Andrew Waterman
1
-0
/
+13
2021-06-01
Test all four ways of reading a read-only CSR
Andrew Waterman
1
-0
/
+8
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