rocket-tools/riscv-tests.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
ceasetest2	Check basic debugging still works in CeaseMulti	Tim Newsome	20 months
debug	Add debug statement.	Tim Newsome	4 years
debug_disassemble	debug: On failure, disassemble close instructions.	Tim Newsome	22 months
disable_unavailable	debug: Disable Unavailable tests.	Tim Newsome	9 months
master	debug: update lds to merge more section (#573)	Mark Zhuang	8 hours
misc	Make newer version of pylint happy.	Tim Newsome	5 years
python3	Move to Python 3.	Tim Newsome	5 years
riscv-tests-sail	removed the env/ directory, which was a submodule dir. replaced at a higher l...	William McSpaddden	2 months
tmp	tmp	Andrew Waterman	5 years
trigger_priority	Remove ineffective tests.	Tim Newsome	2 years
[...]


Age	Commit message	Author	Files	Lines
2020-03-05	Add debug statement.debug	Tim Newsome	1	-0/+1
2020-03-05	Clean up gdb parsing code. (#247)	Tim Newsome	1	-42/+32
2020-03-05	Add a simple mechanism to skip tests on targets. (#251)	Tim Newsome	2	-1/+9
2020-03-02	enable rv32e compatability by replacing reg x29 with reg x7 (#250)	Cedric Orban	1	-12/+12
2020-02-27	bump env	Andrew Waterman	1	-10/+5
2020-02-21	scall: make the intention of the test in machine mode more clear (#246)	Nils Asmussen	1	-1/+6
2020-02-20	Fix rv64mi-p-csr on systems with FPUs	Andrew Waterman	1	-2/+3
2020-02-14	Add tests for vector register access (#244)	Tim Newsome	5	-34/+137
2020-02-11	Generate very different values on different harts. (#238)	Tim Newsome	2	-4/+5
2020-02-11	Run OpenOCD output through spike-dasm. (#239)	Tim Newsome	1	-3/+9
[...]