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AgeCommit message (Expand)AuthorFilesLines
2020-09-22Separate build of spike and spike-dasmAndrew Waterman1-1296/+0
2020-09-08rvv: disasm: separate vvm and vvChih-Min Chao1-14/+44
2020-09-08rvv: disasm: fix vamoadd nameChih-Min Chao1-1/+1
2020-08-31rvv: disasm: fix amo sub-opcodeChih-Min Chao1-5/+4
2020-08-31rvv: disasm: fix whole loadChih-Min Chao1-3/+10
2020-08-31rvv: add reciprocal instructionsChih-Min Chao1-0/+2
2020-08-27rvv: remove quad instructionsChih-Min Chao1-4/+0
2020-07-29rvv: add vrgatherei16.vvChih-Min Chao1-13/+14
2020-07-29rvv: add new whole reg load/store instructionsChih-Min Chao1-2/+25
2020-07-29rvv: op: fix amo namingChih-Min Chao1-4/+4
2020-07-29rvv: disasm: fix missing vamoorei operandsChih-Min Chao1-1/+2
2020-07-21Remove deprecated decoding of xor x0,x0,x0Andrew Waterman1-1/+0
2020-06-16Merge pull request #490 from chihminchao/rvv-fix-2020-06-17Andrew Waterman1-1/+1
2020-06-16rvv: disasm: fix vwadd.wx operandChih-Min Chao1-1/+1
2020-06-16zfh: disasm: add fp16 disasmChih-Min Chao1-0/+38
2020-06-11rvv: disasm: fix vfncvt.f.f.wChih-Min Chao1-1/+1
2020-05-28rvv: add new explicit eew load/store instructionsChih-Min Chao1-64/+51
2020-05-28rvv: add amo instructionsChih-Min Chao1-0/+50
2020-05-28rvv: add new singed/unsiged extension instructionsChih-Min Chao1-0/+8
2020-05-28rvv: extenc VU structure to support 0.9 new fieldsChih-Min Chao1-2/+23
2020-05-28rvv: op: change funary opChih-Min Chao1-3/+9
2020-05-28rvv: disasm: add missing .wx formatChih-Min Chao1-1/+3
2020-05-04rvv: fp16: support conversion instrucitonsChih-Min Chao1-2/+2
2020-04-24rvv: disasm: leave only SEW-bit segment load/storeChih-Min Chao1-66/+0
2020-04-24rvv: add vfslide1[down|up].vf and refine checking ruleChih-Min Chao1-0/+2
2020-04-20rvv: add float conversion for rtz variantsChih-Min Chao1-1/+7
2020-02-05Fix immediate signedness in vector disassemblyAndrew Waterman1-3/+3
2020-01-13rvv: add vmv[1248]r.vChih-Min Chao1-4/+9
2020-01-13rvv: fix vfwcvt/vfncvt for f32 -> f64 and f64 -> f32Chih-Min Chao1-11/+9
2019-12-20rvv: replace vn suffic by 'w'Chih-Min Chao1-26/+30
2019-12-20rvv: add load/store whole register instructionsChih-Min Chao1-11/+15
2019-12-20rvv: rename vfncvt suffix and add rod rouding typeChih-Min Chao1-15/+21
2019-12-20rvv: add quad insn and new vlenb csrChih-Min Chao1-5/+5
2019-11-15add vaaddu/vasubu/vfncvt.rod.f.f.v to diassemblerAndrew Waterman1-2/+5
2019-10-29rvv: remove vmfordChih-Min Chao1-1/+0
2019-10-07Speed up compilation of disasm.cc, especially in clangAndrew Waterman1-1/+1
2019-08-23Fix c.fldsp/c.fsdsp disassembly bugAndrew Waterman1-2/+2
2019-07-19vext.x.v -> vmv.x.s; unary operation encoding changesAndrew Waterman1-1/+1
2019-07-05vmfirst/vmpopc have been renamed to vfirst/vpopcAndrew Waterman1-2/+2
2019-06-14rvv: disasm: add v-spec 0.7.1 supportChih-Min Chao1-0/+517
2018-10-03fix disassembly of c.addi4spnAndrew Waterman1-1/+1
2018-08-23Fix several disassembler bugsAndrew Waterman1-57/+88
2018-01-03Add some missing RVC instructions to disassemblerAndrew Waterman1-0/+3
2017-11-06Implement Q extension for disassembler (#153)Kito Cheng1-0/+36
2017-11-03Fix disassembly of c.li 0Andrew Waterman1-1/+1
2017-08-10Correct c.li and c.lui disassembly (#118)Palmer Dabbelt1-2/+2
2017-04-25FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.XAndrew Waterman1-2/+2
2017-04-25Remove hret instructionAndrew Waterman1-1/+0
2016-06-29Disassemble RVC instructions based on XLENAndrew Waterman1-8/+18
2016-06-03Minor usability improvements (#48)neuschaefer1-1/+6
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