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path: root/riscv/processor.h
AgeCommit message (Expand)AuthorFilesLines
2022-05-12Remove insn_func_t::supported fieldAndrew Waterman1-5/+1
2022-05-04Implement the new csr mseccfg for ePMP as dummysoberl@nvidia.com1-0/+2
2022-04-14add support for overlap instructionsWeiwei Li1-1/+5
2022-04-11Change processor_t to hold a pointer to an isa_parser_t (#973)Rupert Swarbrick1-5/+5
2022-04-11Merge pull request #944 from riscv-software-src/triggersScott Johnson1-126/+6
2022-04-07Rename processor_t::set_csr to put_csr to fix build on RISC-VAndrew Waterman1-1/+1
2022-04-07Pass ref instead of pointer to trigger_updated()Tim Newsome1-1/+1
2022-04-05Make triggers a vector of trigger_t.Tim Newsome1-1/+1
2022-04-05Make triggers::module_t::triggers private.Tim Newsome1-1/+1
2022-04-05Move num_triggers knowledge into triggers.hTim Newsome1-2/+0
2022-04-05Move trigger_match() into triggers.Tim Newsome1-81/+0
2022-03-30Make a few processor_t members const.Tim Newsome1-3/+3
2022-03-30Move tdata2 into mcontrol_tTim Newsome1-1/+1
2022-03-30Replace state.mcontrol with TM.triggers.Tim Newsome1-11/+11
2022-03-30mcontrol_match_t -> mcontrol_t::match_tTim Newsome1-6/+6
2022-03-30Move mcontrol_t and mcontrol_match_t into triggersTim Newsome1-36/+7
2022-03-30mcontrol_action_t -> triggers::action_tTim Newsome1-10/+1
2022-03-30trigger_operation_t -> triggers::operation_tTim Newsome1-4/+5
2022-03-29Split isa_parser_t out of processor.* and into its own file (#955)Rupert Swarbrick1-74/+1
2022-03-16Inline most implicit accesses to fflags/frmAndrew Waterman1-2/+2
2022-03-12Construct an isa_parser_t and pass it to processor_t constructorRupert Swarbrick1-5/+12
2022-03-11Incorporate supported privilege levels into isa_parser_t (#940)Rupert Swarbrick1-1/+2
2022-03-03Change some methods to take a const isa_parser_t (#939)Rupert Swarbrick1-2/+2
2022-02-26add missed extensions specified by '--extension' to custom_extensionsWeiwei Li1-1/+1
2022-02-23perf: refine csr accessibility checkingChih-Min Chao1-0/+2
2022-02-18Split out MINSTRET and MCYCLERupert Swarbrick1-0/+1
2022-02-18Rename minstret CSR classes to something more generalRupert Swarbrick1-1/+1
2022-02-17Split Xbitmanip into its proposed component extensions (#918)Rupert Swarbrick1-1/+8
2022-02-16Merge branch 'plct-cmo-upstream' of https://github.com/plctlab/plct-spike int...Andrew Waterman1-0/+7
2022-01-29add isa string, csr support for cmo extensionsliweiwei1-0/+7
2022-01-27add disas support for zfinx, zdinx and zhinx{min}Weiwei Li1-0/+4
2022-01-26Use unified ISA-string processing in spike-dasm and spikeWeiwei Li1-8/+21
2022-01-06Support RV32E/RV64E base ISAsAndrew Waterman1-9/+12
2022-01-06DRY in illegal-instruction descriptorsAndrew Waterman1-2/+7
2022-01-06DRY in selecting instruction functionsAndrew Waterman1-0/+2
2021-12-07Add 'Zfhmin' extension (#880)Tsukasa #01 (a4lg)1-0/+1
2021-10-14Split 'P' to EXT_ZPN and friends (#830)marcfedorow1-0/+4
2021-10-06Make vxsat into its own classScott Johnson1-2/+3
2021-09-29Convert vtype to csr_tScott Johnson1-3/+3
2021-09-29Convert vl to csr_tScott Johnson1-3/+3
2021-09-29Convert vxrm to csr_tScott Johnson1-4/+4
2021-09-29Convert vstart to csr_tScott Johnson1-3/+3
2021-09-29Convert vxsat to csr_tScott Johnson1-2/+3
2021-09-29Initialize vectorUnit_t attributes to avoid Valgrind warningsScott Johnson1-2/+20
2021-09-28Convert sentropy to csr_tScott Johnson1-2/+2
2021-09-27Convert frm & fflags to csr_tScott Johnson1-2/+2
2021-09-26Convert dcsr to csr_tScott Johnson1-1/+1
2021-09-26Move dcsr_t definition to csrs.hScott Johnson1-12/+0
2021-09-26Convert dpc to csr_tScott Johnson1-1/+1
2021-09-26Convert dscratch0/1 to csr_tScott Johnson1-1/+0
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