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AgeCommit message (Expand)AuthorFilesLines
2023-05-18Call stash_privilege more selectivelyrivosinc-etrigger_fix_exception_matchAndrew Waterman1-0/+2
2023-05-17Add last_v to processor stateAtul Khare1-0/+1
2023-05-11Use passed in virtual bit for creating traps in take_trigger_action() rahter ...rbuchner1-1/+1
2023-05-11Plumb in effective virtual bit to take_trigger_action()rbuchner1-1/+1
2023-04-11explicitly show D(-mode) instead of M(-mode) when in debug modeYenHaoChen1-0/+2
2023-04-04Decrement icount trigger count on external interruptScott Johnson1-0/+1
2023-03-29Support zihpm && !zicntrJerry Zhao1-2/+2
2023-03-29Set counteren_mask properly when !(zihpm && zicntr)Jerry Zhao1-1/+1
2023-03-20Implement Smrnmi extensionAndrew Waterman1-3/+16
2023-02-07Merge pull request #1245 from riscv-software-src/misa-c-writableAndrew Waterman1-2/+3
2023-02-06Make JVT CSR definition account for dynamically disabling ZcmtAndrew Waterman1-1/+1
2023-02-06Add infrastructure to dynamically disable multi-letter extensionsWeiwei Li1-1/+2
2023-02-06Use sv57 paging for rv64 configurationsJerry Zhao1-1/+1
2023-02-06Set cfg-provided processor_t.pmp_num before parsing the dtbJerry Zhao1-1/+1
2023-02-04Remove decode_macros.h from disasm.hJerry Zhao1-0/+1
2023-01-30triggers: force to slow path with icount triggersYenHaoChen1-1/+5
2023-01-27Enable Svadu control bits in menvcfg and henvcfgAaron Durbin1-0/+2
2023-01-19Improve PMP number/granularity error messagesAndrew Waterman1-3/+4
2023-01-18Instantiate tdata/tinfo as const csrs when trigger_count == 0Jerry Zhao1-5/+11
2023-01-18Add trigger_count field to cfg_tJerry Zhao1-1/+1
2023-01-03Fix debug-mode regression introduced by 20e7f53Jerry Zhao1-0/+2
2023-01-03Pass cfg object to processor_t constructorAndrew Waterman1-5/+4
2022-12-27Prevent processor_t from retiring instructions after a WFIJerry Zhao1-0/+4
2022-12-21Merge pull request #1192 from riscv-software-src/improve-histogramAndrew Waterman1-2/+6
2022-12-21Sort histogram printout count, rather than addressAndrew Waterman1-2/+6
2022-12-21Remove --enable-histogram optionAndrew Waterman1-7/+0
2022-12-21Support histogram regardless of configure flagAndrew Waterman1-2/+0
2022-12-20Always build with commit logging supportJerry Zhao1-8/+0
2022-12-20Add logged instruction variants to insn_desc_tJerry Zhao1-3/+12
2022-12-20Add logged variants of insn templatesJerry Zhao1-8/+8
2022-12-20Always reset commit logging variablesJerry Zhao1-2/+0
2022-12-20Always perform symbol lookup in debugJerry Zhao1-2/+5
2022-12-15Rename memif_endianness_t to endianness_tJerry Zhao1-1/+1
2022-12-13Merge pull request #1173 from ucb-bar/splitvuAndrew Waterman1-61/+1
2022-12-12Make the processor_t interface independent of configure'd variables (#1174)Jerry Zhao1-2/+8
2022-12-12Pull vector unit into separate source/headerJerry Zhao1-61/+1
2022-12-10triggers: add mcontext and hcontext CSRsYenHaoChen1-0/+3
2022-12-10triggers: add scontext CSRYenHaoChen1-0/+2
2022-12-09refactor: add tdata3_csr_t; preparation for CSR textraYenHaoChen1-1/+1
2022-12-05Merge pull request #1155 from YenHaoChen/pr-h-not-constScott Johnson1-6/+2
2022-12-05add macro N_HPMCOUNTERS (29)YenHaoChen1-1/+1
2022-12-05refactor: add custom CSR class, mevent_csr_tYenHaoChen1-5/+1
2022-12-01triggers: add debug log of trigger actionYenHaoChen1-0/+7
2022-12-01triggers: refactor: add take_trigger_action() to processor.h/processor.ccYenHaoChen1-0/+16
2022-11-29triggers: rename storeTim Newsome1-1/+1
2022-11-29Triggers: rename loadTim Newsome1-1/+1
2022-11-23Triggers rename executeTim Newsome1-1/+1
2022-11-22Add tinfo register.Tim Newsome1-0/+1
2022-11-17add support for zcmtWeiwei Li1-1/+6
2022-11-17add support for zca zcd and zcfWeiwei Li1-1/+1
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