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| author | Andrew Waterman <andrew@sifive.com> | 2023-05-18 21:48:53 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-05-18 21:48:53 -0700 |
| commit | 0e83fe66fbf7b918602476bbaacfa6198a90d337 (patch) | |
| tree | 93a72f8e0f093f1c872a0cacb2d822c166954bc0 /riscv/processor.cc | |
| parent | 7a2ff14bff461f2c7adfbf407e11527f55d920db (diff) | |
| download | riscv-isa-sim-rivosinc-etrigger_fix_exception_match.zip riscv-isa-sim-rivosinc-etrigger_fix_exception_match.tar.gz riscv-isa-sim-rivosinc-etrigger_fix_exception_match.tar.bz2 | |
Call stash_privilege more selectivelyrivosinc-etrigger_fix_exception_match
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 984b9e5..f7cc5fe 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -783,6 +783,8 @@ void processor_t::debug_output_log(std::stringstream *s) void processor_t::take_trap(trap_t& t, reg_t epc) { + stash_privilege(); + unsigned max_xlen = isa->get_max_xlen(); if (debug) { |