| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
|
|
As proposed in #1652, we made the following changes to MMIO device (factory)
plugin API, to mitigate current limitations and facilitate factory reuse.
- removed `sargs` from `device_factory_t`, and introduced a new type alias
`device_factory_sargs_t` to capture `<device_factory_t *, sargs>` pairs,
this is used to instantiate sim_t instances;
- changed the signature of `device_factory_t::generate_fdt` and
`device_factory_t::parse_from_fdt` to take on an extra `sargs` argument,
for instantiating devices with per-device arguments;
- made `device_factory_t` const and potentially resuable across multiple
`sim_t` instances.
|
|
Signed-off-by: Tilmann Bartsch <info@tebartsch.ai>
|
|
"riscv,plic0" and "sifive,plic-1.0.0" in device tree's "compatible" string point to the same driver,
as can be seen from drivers/irqchip/irq-sifive-plic.c in Linux kernel.
https://github.com/torvalds/linux/commit/5873ba559101fa37ad9764e79856f71bf54021aa
The other two "compatible" strings below isn't included,
because of their different plic behavior (plic_edge_init instead of plic_init as explained in the Linux commit).
- "andestech,nceplic100"
- "thead,c900-plic"
Signed-off-by: Tan En De <ende.tan@starfivetech.com>
|
|
|
|
|
|
|
|
|
|
In keeping with the spirit of simif_t.
|
|
|
|
It's safe to overwrite bytes when returning false.
|
|
This commit started as an attempt to make the PLIC tolerant of
discontiguous hart IDs, but it turns out it was already most of
the way there: PLIC contexts can still be dense even if the hart
IDs are not.
Nevertheless, I wanted to avoid passing the procs vector directly to
the plic_t constructor. In removing it, I realized I could also get
rid of the smode parameter by querying whether each hart has S-mode.
This is also more correct; previously, we were instantiating the PLIC
as though all harts had S-mode, regardless of whether they actually did.
|
|
|
|
|
|
|
|
init `max_prio` by initialization-list
|
|
CONTEXT_THRESHOLD`
|
|
Most implementations can't raise precise exceptions as a function of
sub-page addressing, so don't attempt to do so here. Also, support
double-word-sized writes. Although PLICs aren't required to support
this behavior, they are allowed to. Some existing implementations
support this behavior, and some existing software relies upon it
(unfortunately).
|
|
|
|
We need an interrupt controller in Spike which will allow us to
emulate more real-world devices such as UART, VirtIO net, VirtIO
block, etc.
The RISC-V PLIC (or SiFive PLIC) is the commonly used interrupt
controller in existing RISC-V platforms so this patch adds PLIC
emulation for Spike.
Signed-off-by: Anup Patel <anup@brainfault.org>
|
