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The old implementation performed the load before checking whether the
memory region was valid for LR. So, for LR to MMIO, we would action
side effects before raising the exception, which is not precise.
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Co-authored-by: zhongchengyong <zhongcy93@gmail.com>
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Co-authored-by: zhongcy <zhongcy93@gmail.com>
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Fixes https://github.com/riscv/riscv-isa-sim/issues/591
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I think this bug wasn't caught because OS code never steps over faulting
LR instructions in practice. The exception is either fatal (in which case
the point is moot) or the LR is re-executed (in which case the point is
also moot).
Resolves #431
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- Use physical addresses to avoid homonym ambiguity (closes #215)
- Yield reservation on store-conditional (https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612)
- Don't yield reservation on exceptions (it's no longer required).
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Default is RV64IMAFDC. Can do things like
--isa=RV32 (which implies IMAFDC)
--isa=IM (which implies RV64)
--isa=RV64IMAFDXhwacha
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