rocket-tools/riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2013-07-25	Remove JALR static hints	Andrew Waterman	1	-3/+0

2011-06-19	temporary undoing of renaming	Andrew Waterman	1	-0/+3

2011-06-12	[sim] renamed to riscv-isa-run	Andrew Waterman	1	-3/+0

2011-06-11	[xcc] instructions now set PC explicitly	Andrew Waterman	1	-3/+3

2011-04-15	[sim] fixed jalr immediate bug	Andrew Waterman	1	-2/+2

2011-01-11	[sim] fix jalr bug	Andrew Waterman	1	-1/+1

2010-11-21	[xcc, sim, pk, opcodes] new instruction encoding!	Andrew Waterman	1	-2/+2

2010-09-20	[xcc, sim] changed instruction format so imm12 subs for rs2	Andrew Waterman	1	-2/+2

2010-07-28	[sim,xcc] Changed instruction format to RISC-V	Andrew Waterman	1	-0/+3
	Massive changes to gcc, binutils to support new instruction encoding. Simulator reflects these changes.