Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2022-11-17 | add support for zca zcd and zcf | Weiwei Li | 1 | -1/+1 | |
2015-09-08 | Improve instruction fetch | Andrew Waterman | 1 | -11/+2 | |
- Performance for variable-length instructions is much better - Refill is simpler and faster - Support for instructions with overlapping opcodes (e.g. C.ADD + C.JALR) | |||||
2015-09-04 | Move towards RVC v1.8 | Andrew Waterman | 1 | -3/+8 | |
2015-05-31 | New RV64C proposal | Andrew Waterman | 1 | -1/+6 | |
2015-04-03 | Support setting ISA/subsets with --isa flag | Andrew Waterman | 1 | -1/+1 | |
Default is RV64IMAFDC. Can do things like --isa=RV32 (which implies IMAFDC) --isa=IM (which implies RV64) --isa=RV64IMAFDXhwacha | |||||
2015-03-30 | Implement RVC draft | Andrew Waterman | 1 | -0/+2 | |
2013-07-26 | Rip out RVC for now | Andrew Waterman | 1 | -2/+0 | |
2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+2 | |
2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -2/+0 | |
2011-04-24 | [xcc,sim,opcodes] added more RVC instructions | Andrew Waterman | 1 | -0/+2 | |