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2022-07-21Merge pull request #1040 from plctlab/plct-priv-devAndrew Waterman1-19/+24
2022-07-21add base verify_permission in counter_proxy_csr_t::verify_permissionsWeiwei Li1-1/+3
2022-07-21add support for time/timeh/htimedelta/htimedeltah csrsWeiwei Li1-0/+19
2022-07-21modify minstret/mcycle/minstreth/mcycleh to reuse rv32_low/high_csr_tWeiwei Li1-25/+9
2022-07-18Merge pull request #1041 from plctlab/plct-new-csrsAndrew Waterman1-11/+15
2022-07-17modify the check for "state->prv >= PRV_M" to "state->prv == PRV_M"Weiwei Li1-1/+1
2022-07-17Fix the initial value and write mask for mstatusWeiwei Li1-2/+6
2022-07-17remove unnecessary ifdef for RISCV_ENABLE_DUAL_ENDIANWeiwei Li1-2/+0
2022-07-17extract the progress of computing the inital value of mstatus intoWeiwei Li1-9/+11
2022-07-15Merge pull request #1043 from YenHaoChen/pr-conditionalize-epmpAndrew Waterman1-0/+6
2022-07-13Properly log mstatush side effect updatesScott Johnson1-1/+3
2022-07-13Add assertion to ensure proper logging of mstatus changes on RV32Scott Johnson1-0/+4
2022-07-13Add proxy for accessing the low 32 bits of a 64-bit CSRScott Johnson1-0/+18
2022-07-13Remove no-longer-needed mask from rv32_high_csr_tScott Johnson1-2/+2
2022-07-13Remove unnecessary mask from rv32_high_csr_t constructorScott Johnson1-3/+2
2022-07-13add check for H extension requires S mode (#1042)liweiwei901-1/+1
2022-07-13Add verify_permissions() for mseccfg_csr_tYenHaoChen1-0/+6
2022-07-11Merge pull request #1035 from plctlab/plct-smstateen-devAndrew Waterman1-71/+124
2022-07-11Allow writes to pmp(i-1)cfg on locked pmp(i)cfg (#1039)YenHaoChen1-1/+1
2022-07-09add smstateen check for fcsr, senvcfg, henvcfgWeiwei Li1-0/+40
2022-07-09add standalone class for fcsr and senvcfg csrWeiwei Li1-0/+11
2022-07-09add support for csrs of smstateen extensionsWeiwei Li1-0/+61
2022-07-07modify mstatush_csr_t to general rv32_high_csr_tWeiwei Li1-8/+12
2022-07-07remove multi blank linesWeiwei Li1-63/+0
2022-05-26Fix RV32 hgatp write mask computation (#1014)Andrew Waterman1-1/+1
2022-05-11Change henvcfg csr to a henvcfg_csr_tRyan Buchner1-0/+7
2022-05-04Update pmpaddr_csr_t::access_ok() for ePMP on matching regionssoberl@nvidia.com1-5/+31
2022-05-04Update csr access rules for ePMP on pmpaddr and pmpcfgsoberl@nvidia.com1-7/+31
2022-05-04Implement the new csr mseccfg for ePMP as dummysoberl@nvidia.com1-0/+43
2022-04-11Merge pull request #944 from riscv-software-src/triggersScott Johnson1-56/+7
2022-04-11Fix hgatp CSR writeAnup Patel1-1/+1
2022-04-06mmu: support asid/vmid (#928)Chih-Min Chao1-3/+8
2022-04-05Merge pull request #960 from marcfedorow/upstreamAndrew Waterman1-6/+13
2022-04-05Move num_triggers knowledge into triggers.hTim Newsome1-1/+1
2022-04-05Don't access triggers vector directly from csrs.cc.Tim Newsome1-4/+4
2022-04-05Move tdata2 logic into trigger.Tim Newsome1-6/+2
2022-04-05Make misa.V writableMark Fedorov1-1/+3
2022-04-05Since ca08503 this code only runs at reset, so no longer depends on misa.V be...Mark Fedorov1-2/+2
2022-04-04Make misa.Q writableMark Fedorov1-1/+3
2022-04-04Refactor misa maskingMark Fedorov1-3/+6
2022-03-30Move tdata1 write logic into triggers.Tim Newsome1-23/+1
2022-03-30Move tdata1 read logic into triggers.cc.Tim Newsome1-19/+1
2022-03-30Move tdata2 into mcontrol_tTim Newsome1-9/+4
2022-03-30Replace state.mcontrol with TM.triggers.Tim Newsome1-3/+3
2022-03-30mcontrol_match_t -> mcontrol_t::match_tTim Newsome1-1/+1
2022-03-30Move mcontrol_t and mcontrol_match_t into triggersTim Newsome1-3/+3
2022-03-30mcontrol_action_t -> triggers::action_tTim Newsome1-1/+1
2022-03-30Implement Sv57 and Sv57x4 translation modesAndrew Waterman1-1/+3
2022-03-30Don't allow hgatp.MODE to be set to Sv48x4 unless implementedAndrew Waterman1-2/+2
2022-03-16Raise illegal (not virtual) instruction exception on counter writes (#951)Andrew Waterman1-4/+1
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