index
:
rocket-tools/riscv-isa-sim.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
Branch
Commit message
Author
Age
device_flags
Allow device flags after --device cmdline arg
Jerry Zhao
10 months
dts_parsing
Support parsing procs fully from DTS
Jerry Zhao
3 months
dynamic
build: Dynamically link installed progs
Jerry Zhao
15 months
fix-bf16
Add f64_to_bf16; fix f32_to_bf16
Andrew Waterman
18 months
force-rtti
build: Include all symbols from extension.o when linking spike's main
Jerry Zhao
15 months
log-commits-faster
tmp
Andrew Waterman
11 months
master
Merge pull request #1829 from NXP/update-zilsd-to-v0.10
Andrew Waterman
8 days
nolibfdt
Remove in-tree libfdt, rely on system-installed libfdt
Jerry Zhao
10 months
rivosinc-etrigger_fix_exception_match
Call stash_privilege more selectively
Andrew Waterman
17 months
whole-archive
build: Link spike binaries with --whole-archive
Jerry Zhao
15 months
[...]
Tag
Download
Author
Age
dummy-tag-for-ci-storage
riscv-isa-sim-dummy-tag-for-ci-storage.zip
riscv-isa-sim-dummy-tag-for-ci-storage.tar.gz
riscv-isa-sim-dummy-tag-for-ci-storage.tar.bz2
Andrew Waterman
2 years
v1.1.0
riscv-isa-sim-1.1.0.zip
riscv-isa-sim-1.1.0.tar.gz
riscv-isa-sim-1.1.0.tar.bz2
Andrew Waterman
3 years
v1.0.0
riscv-isa-sim-1.0.0.zip
riscv-isa-sim-1.0.0.tar.gz
riscv-isa-sim-1.0.0.tar.bz2
Andrew Waterman
6 years
Age
Commit message
Author
Files
Lines
2022-07-30
Move fence inside entry_loop.
debug_rom_fence
Tim Newsome
2
-5
/
+4
2022-07-30
DSCRATCH is now called DSCRATCH0
Tim Newsome
1
-4
/
+4
2022-07-30
Fix debug_rom.S build command error.
Tim Newsome
1
-1
/
+1
2022-07-25
Pay attention to dmcs2.grouptype. (#1049)
Tim Newsome
1
-1
/
+3
2022-07-21
Merge pull request #1040 from plctlab/plct-priv-dev
Andrew Waterman
5
-31
/
+59
2022-07-21
add base verify_permission in counter_proxy_csr_t::verify_permissions
Weiwei Li
1
-1
/
+3
2022-07-21
add support for time/timeh/htimedelta/htimedeltah csrs
Weiwei Li
5
-0
/
+49
2022-07-21
modify minstret/mcycle/minstreth/mcycleh to reuse rv32_low/high_csr_t
Weiwei Li
3
-44
/
+21
2022-07-18
Fix load/store performance under clang
Andrew Waterman
2
-2
/
+4
2022-07-18
Merge pull request #1041 from plctlab/plct-new-csrs
Andrew Waterman
5
-37
/
+44
[...]