diff options
Diffstat (limited to 'riscv')
294 files changed, 0 insertions, 3385 deletions
diff --git a/riscv/applink.cc b/riscv/applink.cc deleted file mode 100644 index e3e979d..0000000 --- a/riscv/applink.cc +++ /dev/null @@ -1,154 +0,0 @@ -#include "applink.h" -#include "common.h" -#include "sim.h" -#include <unistd.h> -#include <stdexcept> - -enum -{ - APP_CMD_READ_MEM, - APP_CMD_WRITE_MEM, - APP_CMD_READ_CONTROL_REG, - APP_CMD_WRITE_CONTROL_REG, - APP_CMD_START, - APP_CMD_STOP, - APP_CMD_ACK, - APP_CMD_NACK -}; - -#define APP_DATA_ALIGN 8 -#define APP_MAX_DATA_SIZE 1024 -struct packet -{ - uint16_t cmd; - uint16_t seqno; - uint32_t data_size; - uint64_t addr; - uint8_t data[APP_MAX_DATA_SIZE]; -}; - -class packet_error : public std::runtime_error -{ -public: - packet_error(const std::string& s) : std::runtime_error(s) {} -}; -class io_error : public packet_error -{ -public: - io_error(const std::string& s) : packet_error(s) {} -}; - -appserver_link_t::appserver_link_t(int _tohost_fd, int _fromhost_fd) - : sim(NULL), tohost_fd(_tohost_fd), fromhost_fd(_fromhost_fd), seqno(1) -{ -} - -void appserver_link_t::init(sim_t* _sim) -{ - sim = _sim; -} - -void appserver_link_t::wait_for_start() -{ - while(wait_for_packet() != APP_CMD_START); -} - -void appserver_link_t::wait_for_tohost() -{ - while(wait_for_packet() != APP_CMD_READ_CONTROL_REG); -} - -void appserver_link_t::wait_for_fromhost() -{ - while(wait_for_packet() != APP_CMD_WRITE_CONTROL_REG); -} - -void appserver_link_t::send_packet(packet* p) -{ - while(1) try - { - int bytes = write(tohost_fd,p,offsetof(packet,data)+p->data_size); - if(bytes == -1 || (size_t)bytes != offsetof(packet,data)+p->data_size) - throw io_error("write failed"); - return; - } - catch(io_error e) - { - fprintf(stderr,"warning: %s\n",e.what()); - } -} - -void appserver_link_t::nack(uint16_t nack_seqno) -{ - packet p = {APP_CMD_NACK,nack_seqno,0,0}; - send_packet(&p); -} - -int appserver_link_t::wait_for_packet() -{ - while(1) try - { - packet p; - int bytes = read(fromhost_fd,&p,sizeof(p)); - if(bytes < (signed)offsetof(packet,data)) - throw io_error("read failed"); - - if(p.seqno != seqno) - { - nack(p.seqno); - continue; - } - - packet ackpacket = {APP_CMD_ACK,seqno,0,0}; - - switch(p.cmd) - { - case APP_CMD_START: - break; - case APP_CMD_STOP: - send_packet(&ackpacket); - throw quit_sim(); - case APP_CMD_READ_MEM: - demand(p.addr % APP_DATA_ALIGN == 0, "misaligned address"); - demand(p.data_size % APP_DATA_ALIGN == 0, "misaligned data"); - demand(p.data_size <= APP_MAX_DATA_SIZE, "long read data"); - demand(p.addr <= sim->memsz && p.addr+p.data_size <= sim->memsz, "out of bounds: 0x%llx",(unsigned long long)p.addr); - ackpacket.data_size = p.data_size; - - static_assert(APP_DATA_ALIGN >= sizeof(uint64_t)) - for(size_t i = 0; i < p.data_size/8; i++) - ((uint64_t*)ackpacket.data)[i] = sim->mmu->load_uint64(p.addr+i*8); - break; - case APP_CMD_WRITE_MEM: - demand(p.addr % APP_DATA_ALIGN == 0, "misaligned address"); - demand(p.data_size % APP_DATA_ALIGN == 0, "misaligned data"); - demand(p.data_size <= bytes - offsetof(packet,data), "short packet"); - demand(p.addr <= sim->memsz && p.addr+p.data_size <= sim->memsz, "out of bounds: 0x%llx",(unsigned long long)p.addr); - - for(size_t i = 0; i < p.data_size/8; i++) - sim->mmu->store_uint64(p.addr+i*8, ((uint64_t*)p.data)[i]); - break; - case APP_CMD_READ_CONTROL_REG: - demand(p.addr == 16,"bad control reg"); - demand(p.data_size == sizeof(reg_t),"bad control reg size"); - ackpacket.data_size = sizeof(reg_t); - memcpy(ackpacket.data,&sim->tohost,sizeof(reg_t)); - break; - case APP_CMD_WRITE_CONTROL_REG: - demand(p.addr == 17,"bad control reg"); - demand(p.data_size == sizeof(reg_t),"bad control reg size"); - sim->tohost = 0; - memcpy(&sim->fromhost,p.data,sizeof(reg_t)); - break; - } - - send_packet(&ackpacket); - seqno++; - return p.cmd; - } - catch(io_error e) - { - fprintf(stderr,"warning: %s\n",e.what()); - } -} - diff --git a/riscv/applink.h b/riscv/applink.h deleted file mode 100644 index 5ef0a1a..0000000 --- a/riscv/applink.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef _APPLINK_H -#define _APPLINK_H - -#include <stdint.h> - -class sim_t; -struct packet; -class appserver_link_t -{ -public: - appserver_link_t(int _tohost_fd, int _fromhost_fd); - void init(sim_t* _sim); - void wait_for_start(); - void wait_for_tohost(); - void wait_for_fromhost(); - int wait_for_packet(); - -private: - sim_t* sim; - int tohost_fd; - int fromhost_fd; - uint16_t seqno; - - void nack(uint16_t seqno); - void send_packet(packet* p); -}; - -#endif diff --git a/riscv/common.h b/riscv/common.h deleted file mode 100644 index 7dd6570..0000000 --- a/riscv/common.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef _RISCV_COMMON_H -#define _RISCV_COMMON_H - -#include <stdio.h> -#include <string.h> -#include <stdlib.h> - -#ifdef __cplusplus -# include <stdexcept> -# define print_and_die(s) throw std::runtime_error(s) -#else -# define print_and_die(s) do { fprintf(stderr,"%s\n",s); abort(); } while(0) -#endif - -#define demand(cond,str,...) \ - do { if(!(cond)) { \ - char __str[256]; \ - snprintf(__str,256,"in %s, line %d: " str, \ - __FILE__,__LINE__,##__VA_ARGS__); \ - print_and_die(__str); \ - } } while(0) - -#define static_assert(x) switch (x) case 0: case (x): - -#define likely(x) __builtin_expect(x, 1) -#define unlikely(x) __builtin_expect(x, 0) - -#endif diff --git a/riscv/decode.h b/riscv/decode.h deleted file mode 100644 index 2078e58..0000000 --- a/riscv/decode.h +++ /dev/null @@ -1,301 +0,0 @@ -#ifndef _RISCV_DECODE_H -#define _RISCV_DECODE_H - -#define __STDC_LIMIT_MACROS -#include <stdint.h> - -#include "config.h" - -typedef int int128_t __attribute__((mode(TI))); -typedef unsigned int uint128_t __attribute__((mode(TI))); - -typedef int64_t sreg_t; -typedef uint64_t reg_t; -typedef uint64_t freg_t; - -const int OPCODE_BITS = 7; - -const int XPRID_BITS = 5; -const int NXPR = 1 << XPRID_BITS; - -const int FPR_BITS = 64; -const int FPRID_BITS = 5; -const int NFPR = 1 << FPRID_BITS; - -const int IMM_BITS = 12; -const int IMMLO_BITS = 7; -const int TARGET_BITS = 25; -const int FUNCT_BITS = 3; -const int FUNCTR_BITS = 7; -const int FFUNCT_BITS = 2; -const int RM_BITS = 3; -const int BIGIMM_BITS = 20; -const int BRANCH_ALIGN_BITS = 1; -const int JUMP_ALIGN_BITS = 1; - -#define SR_ET 0x0000000000000001ULL -#define SR_EF 0x0000000000000002ULL -#define SR_EV 0x0000000000000004ULL -#define SR_EC 0x0000000000000008ULL -#define SR_PS 0x0000000000000010ULL -#define SR_S 0x0000000000000020ULL -#define SR_UX 0x0000000000000040ULL -#define SR_SX 0x0000000000000080ULL -#define SR_IM 0x000000000000FF00ULL -#define SR_VM 0x0000000000010000ULL -#define SR_ZERO ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_UX|SR_SX|SR_IM|SR_VM) -#define SR_IM_SHIFT 8 -#define IPI_IRQ 5 -#define TIMER_IRQ 7 - -#define CAUSE_EXCCODE 0x000000FF -#define CAUSE_IP 0x0000FF00 -#define CAUSE_EXCCODE_SHIFT 0 -#define CAUSE_IP_SHIFT 8 - -#define FP_RD_NE 0 -#define FP_RD_0 1 -#define FP_RD_DN 2 -#define FP_RD_UP 3 -#define FP_RD_NMM 4 - -#define FSR_RD_SHIFT 5 -#define FSR_RD (0x7 << FSR_RD_SHIFT) - -#define FPEXC_NX 0x01 -#define FPEXC_UF 0x02 -#define FPEXC_OF 0x04 -#define FPEXC_DZ 0x08 -#define FPEXC_NV 0x10 - -#define FSR_AEXC_SHIFT 0 -#define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT) -#define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT) -#define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT) -#define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) -#define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) -#define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) - -#define FSR_ZERO ~(FSR_RD | FSR_AEXC) - -// note: bit fields are in little-endian order -struct itype_t -{ - unsigned opcode : OPCODE_BITS; - unsigned funct : FUNCT_BITS; - signed imm12 : IMM_BITS; - unsigned rs1 : XPRID_BITS; - unsigned rd : XPRID_BITS; -}; - -struct btype_t -{ - unsigned opcode : OPCODE_BITS; - unsigned funct : FUNCT_BITS; - unsigned immlo : IMMLO_BITS; - unsigned rs2 : XPRID_BITS; - unsigned rs1 : XPRID_BITS; - signed immhi : IMM_BITS-IMMLO_BITS; -}; - -struct jtype_t -{ - unsigned jump_opcode : OPCODE_BITS; - signed target : TARGET_BITS; -}; - -struct rtype_t -{ - unsigned opcode : OPCODE_BITS; - unsigned funct : FUNCT_BITS; - unsigned functr : FUNCTR_BITS; - unsigned rs2 : XPRID_BITS; - unsigned rs1 : XPRID_BITS; - unsigned rd : XPRID_BITS; -}; - -struct ltype_t -{ - unsigned opcode : OPCODE_BITS; - unsigned bigimm : BIGIMM_BITS; - unsigned rd : XPRID_BITS; -}; - -struct ftype_t -{ - unsigned opcode : OPCODE_BITS; - unsigned ffunct : FFUNCT_BITS; - unsigned rm : RM_BITS; - unsigned rs3 : FPRID_BITS; - unsigned rs2 : FPRID_BITS; - unsigned rs1 : FPRID_BITS; - unsigned rd : FPRID_BITS; -}; - -union insn_t -{ - itype_t itype; - jtype_t jtype; - rtype_t rtype; - btype_t btype; - ltype_t ltype; - ftype_t ftype; - uint32_t bits; -}; - -#include <stdio.h> -class do_writeback -{ -public: - do_writeback(reg_t* _rf, int _rd) : rf(_rf), rd(_rd) {} - - const do_writeback& operator = (reg_t rhs) - { -#if 0 - printf("R[%x] <= %llx\n",rd,(long long)rhs); -#endif - rf[rd] = rhs; - rf[0] = 0; - return *this; - } - - operator reg_t() { return rf[rd]; } - -private: - reg_t* rf; - int rd; -}; - -#define throw_illegal_instruction \ - ({ if (utmode) throw trap_vector_illegal_instruction; \ - else throw trap_illegal_instruction; }) - -// helpful macros, etc -#define RS1 XPR[insn.rtype.rs1] -#define RS2 XPR[insn.rtype.rs2] -#define RD do_writeback(XPR,insn.rtype.rd) -#define RA do_writeback(XPR,1) -#define FRS1 FPR[insn.ftype.rs1] -#define FRS2 FPR[insn.ftype.rs2] -#define FRS3 FPR[insn.ftype.rs3] -#define FRD FPR[insn.ftype.rd] -#define BIGIMM insn.ltype.bigimm -#define SIMM insn.itype.imm12 -#define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS)) -#define SHAMT (insn.itype.imm12 & 0x3F) -#define SHAMTW (insn.itype.imm12 & 0x1F) -#define TARGET insn.jtype.target -#define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS)) -#define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS)) -#define RM ({ int rm = insn.ftype.rm; \ - if(rm == 7) rm = (fsr & FSR_RD) >> FSR_RD_SHIFT; \ - if(rm > 4) throw_illegal_instruction; \ - rm; }) - -#define require_supervisor if(unlikely(!(sr & SR_S))) throw trap_privileged_instruction -#define xpr64 (xprlen == 64) -#define require_xpr64 if(unlikely(!xpr64)) throw_illegal_instruction -#define require_xpr32 if(unlikely(xpr64)) throw_illegal_instruction -#define require_fp if(unlikely(!(sr & SR_EF))) throw trap_fp_disabled -#define require_vector \ - ({ if(!(sr & SR_EV)) throw trap_vector_disabled; \ - else if (!utmode && (vecbanks_count < 3)) throw trap_vector_bank; \ - }) -#define cmp_trunc(reg) (reg_t(reg) << (64-xprlen)) -#define set_fp_exceptions ({ set_fsr(fsr | \ - (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \ - softfloat_exceptionFlags = 0; }) - -#define sext32(x) ((sreg_t)(int32_t)(x)) -#define zext32(x) ((reg_t)(uint32_t)(x)) -#define sext_xprlen(x) ((sreg_t(x) << (64-xprlen)) >> (64-xprlen)) -#define zext_xprlen(x) ((reg_t(x) << (64-xprlen)) >> (64-xprlen)) - -#ifndef RISCV_ENABLE_RVC -# define set_pc(x) \ - do { if((x) & (sizeof(insn_t)-1)) \ - { badvaddr = (x); throw trap_instruction_address_misaligned; } \ - npc = (x); \ - } while(0) -#else -# define set_pc(x) \ - do { if((x) & ((sr & SR_EC) ? 1 : 3)) \ - { badvaddr = (x); throw trap_instruction_address_misaligned; } \ - npc = (x); \ - } while(0) -#endif - -// RVC stuff - -#define INSN_IS_RVC(x) (((x) & 0x3) < 0x3) -#define insn_length(x) (INSN_IS_RVC(x) ? 2 : 4) -#define require_rvc if(!(sr & SR_EC)) throw_illegal_instruction - -#define CRD_REGNUM ((insn.bits >> 5) & 0x1f) -#define CRD do_writeback(XPR, CRD_REGNUM) -#define CRS1 XPR[(insn.bits >> 10) & 0x1f] -#define CRS2 XPR[(insn.bits >> 5) & 0x1f] -#define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26) -#define CIMM5U ((insn.bits >> 5) & 0x1f) -#define CIMM5 ((int32_t)CIMM5U << 27 >> 27) -#define CIMM10 ((int32_t)((insn.bits >> 5) & 0x3ff) << 22 >> 22) -#define CBRANCH_TARGET (pc + (CIMM5 << BRANCH_ALIGN_BITS)) -#define CJUMP_TARGET (pc + (CIMM10 << JUMP_ALIGN_BITS)) - -static const int rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 }; -#define rvc_rd_regmap rvc_rs1_regmap -#define rvc_rs2b_regmap rvc_rs1_regmap -static const int rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 }; -#define CRDS XPR[rvc_rd_regmap[(insn.bits >> 13) & 0x7]] -#define FCRDS FPR[rvc_rd_regmap[(insn.bits >> 13) & 0x7]] -#define CRS1S XPR[rvc_rs1_regmap[(insn.bits >> 10) & 0x7]] -#define CRS2S XPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]] -#define CRS2BS XPR[rvc_rs2b_regmap[(insn.bits >> 5) & 0x7]] -#define FCRS2S FPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]] - -// vector stuff -#define VL vl - -#define UT_RS1(idx) uts[idx]->XPR[insn.rtype.rs1] -#define UT_RS2(idx) uts[idx]->XPR[insn.rtype.rs2] -#define UT_RD(idx) do_writeback(uts[idx]->XPR,insn.rtype.rd) -#define UT_RA(idx) do_writeback(uts[idx]->XPR,1) -#define UT_FRS1(idx) uts[idx]->FPR[insn.ftype.rs1] -#define UT_FRS2(idx) uts[idx]->FPR[insn.ftype.rs2] -#define UT_FRS3(idx) uts[idx]->FPR[insn.ftype.rs3] -#define UT_FRD(idx) uts[idx]->FPR[insn.ftype.rd] -#define UT_RM(idx) ((insn.ftype.rm != 7) ? insn.ftype.rm : \ - ((uts[idx]->fsr & FSR_RD) >> FSR_RD_SHIFT)) - -#define UT_LOOP_START for (int i=0;i<VL; i++) { -#define UT_LOOP_END } -#define UT_LOOP_RS1 UT_RS1(i) -#define UT_LOOP_RS2 UT_RS2(i) -#define UT_LOOP_RD UT_RD(i) -#define UT_LOOP_RA UT_RA(i) -#define UT_LOOP_FRS1 UT_FRS1(i) -#define UT_LOOP_FRS2 UT_FRS2(i) -#define UT_LOOP_FRS3 UT_FRS3(i) -#define UT_LOOP_FRD UT_FRD(i) -#define UT_LOOP_RM UT_RM(i) - -#define VEC_LOAD(dst, func, inc) \ - reg_t addr = RS1; \ - UT_LOOP_START \ - UT_LOOP_##dst = mmu.func(addr); \ - addr += inc; \ - UT_LOOP_END - -#define VEC_STORE(src, func, inc) \ - reg_t addr = RS1; \ - UT_LOOP_START \ - mmu.func(addr, UT_LOOP_##src); \ - addr += inc; \ - UT_LOOP_END - -enum vt_command_t -{ - vt_command_stop, -}; - -#endif diff --git a/riscv/dispatch b/riscv/dispatch deleted file mode 100755 index b96b364..0000000 --- a/riscv/dispatch +++ /dev/null @@ -1,77 +0,0 @@ -#!/usr/bin/python -import sys - -if len(sys.argv) == 3: - numfiles = int(sys.argv[1]) - tablesz = int(sys.argv[2]) - filenum = numfiles+1 -else: - filenum = int(sys.argv[1]) - numfiles = int(sys.argv[2]) - tablesz = int(sys.argv[3]) - -match = {} -mask = {} -seen = {} -for line in sys.stdin: - (name, mtch, msk) = line.split('(')[1].split(')')[0].split(',') - match[name] = int(mtch,16) - mask[name] = int(msk,16) - -redundant = {} -for name in match.iterkeys(): - if (mask[name] & (tablesz-1)) == mask[name]: - for i in range(match[name]+1, tablesz): - if (i & mask[name]) == match[name]: - redundant[i] = match[name] - -illegal = -1 -for i in range(0, tablesz): - used = 0 - for name in match.iterkeys(): - if match[name] % tablesz == (i & mask[name]): - used = 1 - if not used and illegal == -1: - illegal = i - elif not used: - redundant[i] = illegal - -if filenum == numfiles: - print '#include "processor.h"' - print 'const insn_func_t processor_t::dispatch_table[DISPATCH_TABLE_SIZE] = {' - for i in range(0, tablesz): - func = i - if i in redundant: - func = redundant[i] - print ' &processor_t::insn_func_%d,' % func - print '};' - -if filenum == numfiles+1: - print 'static const size_t DISPATCH_TABLE_SIZE = %d;' % tablesz - print 'static const insn_func_t dispatch_table[DISPATCH_TABLE_SIZE];' - for i in range(0, tablesz): - if i not in redundant: - print 'reg_t insn_func_%d(insn_t insn, reg_t reg);' % i - sys.exit(0) - -print '#include "insn_header.h"' - -for i in range(0, tablesz): - if i % numfiles != filenum or i in redundant: - continue - - print 'reg_t processor_t::insn_func_%d(insn_t insn, reg_t pc)' % i - print '{' - for name in match.iterkeys(): - if match[name] % tablesz == (i & mask[name]): - print ' if((insn.bits & 0x%x) == 0x%x)' % (mask[name] & ~(tablesz-1), \ - match[name] & ~(tablesz-1)) - print ' {' - print ' reg_t npc = pc + insn_length(0x%x);' % match[name] - print ' #include "insns/%s.h"' % name - print ' return npc;' - print ' }' - print ' else', - - print ' throw trap_illegal_instruction;' - print '}\n' diff --git a/riscv/dispatch.h b/riscv/dispatch.h deleted file mode 100644 index 7091899..0000000 --- a/riscv/dispatch.h +++ /dev/null @@ -1,254 +0,0 @@ -static const size_t DISPATCH_TABLE_SIZE = 1024; -static const insn_func_t dispatch_table[DISPATCH_TABLE_SIZE]; -reg_t insn_func_0(insn_t insn, reg_t reg); -reg_t insn_func_1(insn_t insn, reg_t reg); -reg_t insn_func_2(insn_t insn, reg_t reg); -reg_t insn_func_3(insn_t insn, reg_t reg); -reg_t insn_func_4(insn_t insn, reg_t reg); -reg_t insn_func_5(insn_t insn, reg_t reg); -reg_t insn_func_6(insn_t insn, reg_t reg); -reg_t insn_func_7(insn_t insn, reg_t reg); -reg_t insn_func_8(insn_t insn, reg_t reg); -reg_t insn_func_9(insn_t insn, reg_t reg); -reg_t insn_func_10(insn_t insn, reg_t reg); -reg_t insn_func_11(insn_t insn, reg_t reg); -reg_t insn_func_12(insn_t insn, reg_t reg); -reg_t insn_func_13(insn_t insn, reg_t reg); -reg_t insn_func_15(insn_t insn, reg_t reg); -reg_t insn_func_16(insn_t insn, reg_t reg); -reg_t insn_func_17(insn_t insn, reg_t reg); -reg_t insn_func_18(insn_t insn, reg_t reg); -reg_t insn_func_19(insn_t insn, reg_t reg); -reg_t insn_func_20(insn_t insn, reg_t reg); -reg_t insn_func_21(insn_t insn, reg_t reg); -reg_t insn_func_22(insn_t insn, reg_t reg); -reg_t insn_func_24(insn_t insn, reg_t reg); -reg_t insn_func_25(insn_t insn, reg_t reg); -reg_t insn_func_26(insn_t insn, reg_t reg); -reg_t insn_func_27(insn_t insn, reg_t reg); -reg_t insn_func_28(insn_t insn, reg_t reg); -reg_t insn_func_29(insn_t insn, reg_t reg); -reg_t insn_func_34(insn_t insn, reg_t reg); -reg_t insn_func_35(insn_t insn, reg_t reg); -reg_t insn_func_50(insn_t insn, reg_t reg); -reg_t insn_func_51(insn_t insn, reg_t reg); -reg_t insn_func_55(insn_t insn, reg_t reg); -reg_t insn_func_57(insn_t insn, reg_t reg); -reg_t insn_func_58(insn_t insn, reg_t reg); -reg_t insn_func_59(insn_t insn, reg_t reg); -reg_t insn_func_66(insn_t insn, reg_t reg); -reg_t insn_func_67(insn_t insn, reg_t reg); -reg_t insn_func_71(insn_t insn, reg_t reg); -reg_t insn_func_75(insn_t insn, reg_t reg); -reg_t insn_func_79(insn_t insn, reg_t reg); -reg_t insn_func_82(insn_t insn, reg_t reg); -reg_t insn_func_83(insn_t insn, reg_t reg); -reg_t insn_func_89(insn_t insn, reg_t reg); -reg_t insn_func_90(insn_t insn, reg_t reg); -reg_t insn_func_98(insn_t insn, reg_t reg); -reg_t insn_func_99(insn_t insn, reg_t reg); -reg_t insn_func_103(insn_t insn, reg_t reg); -reg_t insn_func_107(insn_t insn, reg_t reg); -reg_t insn_func_111(insn_t insn, reg_t reg); -reg_t insn_func_114(insn_t insn, reg_t reg); -reg_t insn_func_115(insn_t insn, reg_t reg); -reg_t insn_func_119(insn_t insn, reg_t reg); -reg_t insn_func_121(insn_t insn, reg_t reg); -reg_t insn_func_122(insn_t insn, reg_t reg); -reg_t insn_func_123(insn_t insn, reg_t reg); -reg_t insn_func_130(insn_t insn, reg_t reg); -reg_t insn_func_131(insn_t insn, reg_t reg); -reg_t insn_func_139(insn_t insn, reg_t reg); -reg_t insn_func_143(insn_t insn, reg_t reg); -reg_t insn_func_146(insn_t insn, reg_t reg); -reg_t insn_func_147(insn_t insn, reg_t reg); -reg_t insn_func_153(insn_t insn, reg_t reg); -reg_t insn_func_154(insn_t insn, reg_t reg); -reg_t insn_func_155(insn_t insn, reg_t reg); -reg_t insn_func_162(insn_t insn, reg_t reg); -reg_t insn_func_163(insn_t insn, reg_t reg); -reg_t insn_func_175(insn_t insn, reg_t reg); -reg_t insn_func_178(insn_t insn, reg_t reg); -reg_t insn_func_179(insn_t insn, reg_t reg); -reg_t insn_func_185(insn_t insn, reg_t reg); -reg_t insn_func_186(insn_t insn, reg_t reg); -reg_t insn_func_187(insn_t insn, reg_t reg); -reg_t insn_func_194(insn_t insn, reg_t reg); -reg_t insn_func_195(insn_t insn, reg_t reg); -reg_t insn_func_199(insn_t insn, reg_t reg); -reg_t insn_func_203(insn_t insn, reg_t reg); -reg_t insn_func_207(insn_t insn, reg_t reg); -reg_t insn_func_210(insn_t insn, reg_t reg); -reg_t insn_func_211(insn_t insn, reg_t reg); -reg_t insn_func_217(insn_t insn, reg_t reg); -reg_t insn_func_218(insn_t insn, reg_t reg); -reg_t insn_func_226(insn_t insn, reg_t reg); -reg_t insn_func_227(insn_t insn, reg_t reg); -reg_t insn_func_235(insn_t insn, reg_t reg); -reg_t insn_func_242(insn_t insn, reg_t reg); -reg_t insn_func_243(insn_t insn, reg_t reg); -reg_t insn_func_247(insn_t insn, reg_t reg); -reg_t insn_func_249(insn_t insn, reg_t reg); -reg_t insn_func_250(insn_t insn, reg_t reg); -reg_t insn_func_251(insn_t insn, reg_t reg); -reg_t insn_func_258(insn_t insn, reg_t reg); -reg_t insn_func_259(insn_t insn, reg_t reg); -reg_t insn_func_263(insn_t insn, reg_t reg); -reg_t insn_func_267(insn_t insn, reg_t reg); -reg_t insn_func_271(insn_t insn, reg_t reg); -reg_t insn_func_274(insn_t insn, reg_t reg); -reg_t insn_func_275(insn_t insn, reg_t reg); -reg_t insn_func_281(insn_t insn, reg_t reg); -reg_t insn_func_282(insn_t insn, reg_t reg); -reg_t insn_func_284(insn_t insn, reg_t reg); -reg_t insn_func_290(insn_t insn, reg_t reg); -reg_t insn_func_291(insn_t insn, reg_t reg); -reg_t insn_func_295(insn_t insn, reg_t reg); -reg_t insn_func_299(insn_t insn, reg_t reg); -reg_t insn_func_303(insn_t insn, reg_t reg); -reg_t insn_func_306(insn_t insn, reg_t reg); -reg_t insn_func_307(insn_t insn, reg_t reg); -reg_t insn_func_313(insn_t insn, reg_t reg); -reg_t insn_func_314(insn_t insn, reg_t reg); -reg_t insn_func_322(insn_t insn, reg_t reg); -reg_t insn_func_338(insn_t insn, reg_t reg); -reg_t insn_func_345(insn_t insn, reg_t reg); -reg_t insn_func_346(insn_t insn, reg_t reg); -reg_t insn_func_354(insn_t insn, reg_t reg); -reg_t insn_func_363(insn_t insn, reg_t reg); -reg_t insn_func_370(insn_t insn, reg_t reg); -reg_t insn_func_371(insn_t insn, reg_t reg); -reg_t insn_func_375(insn_t insn, reg_t reg); -reg_t insn_func_377(insn_t insn, reg_t reg); -reg_t insn_func_378(insn_t insn, reg_t reg); -reg_t insn_func_379(insn_t insn, reg_t reg); -reg_t insn_func_386(insn_t insn, reg_t reg); -reg_t insn_func_387(insn_t insn, reg_t reg); -reg_t insn_func_391(insn_t insn, reg_t reg); -reg_t insn_func_395(insn_t insn, reg_t reg); -reg_t insn_func_399(insn_t insn, reg_t reg); -reg_t insn_func_402(insn_t insn, reg_t reg); -reg_t insn_func_403(insn_t insn, reg_t reg); -reg_t insn_func_409(insn_t insn, reg_t reg); -reg_t insn_func_410(insn_t insn, reg_t reg); -reg_t insn_func_418(insn_t insn, reg_t reg); -reg_t insn_func_419(insn_t insn, reg_t reg); -reg_t insn_func_423(insn_t insn, reg_t reg); -reg_t insn_func_427(insn_t insn, reg_t reg); -reg_t insn_func_434(insn_t insn, reg_t reg); -reg_t insn_func_435(insn_t insn, reg_t reg); -reg_t insn_func_441(insn_t insn, reg_t reg); -reg_t insn_func_442(insn_t insn, reg_t reg); -reg_t insn_func_450(insn_t insn, reg_t reg); -reg_t insn_func_466(insn_t insn, reg_t reg); -reg_t insn_func_473(insn_t insn, reg_t reg); -reg_t insn_func_474(insn_t insn, reg_t reg); -reg_t insn_func_482(insn_t insn, reg_t reg); -reg_t insn_func_498(insn_t insn, reg_t reg); -reg_t insn_func_499(insn_t insn, reg_t reg); -reg_t insn_func_503(insn_t insn, reg_t reg); -reg_t insn_func_505(insn_t insn, reg_t reg); -reg_t insn_func_506(insn_t insn, reg_t reg); -reg_t insn_func_507(insn_t insn, reg_t reg); -reg_t insn_func_514(insn_t insn, reg_t reg); -reg_t insn_func_515(insn_t insn, reg_t reg); -reg_t insn_func_523(insn_t insn, reg_t reg); -reg_t insn_func_530(insn_t insn, reg_t reg); -reg_t insn_func_531(insn_t insn, reg_t reg); -reg_t insn_func_537(insn_t insn, reg_t reg); -reg_t insn_func_538(insn_t insn, reg_t reg); -reg_t insn_func_540(insn_t insn, reg_t reg); -reg_t insn_func_546(insn_t insn, reg_t reg); -reg_t insn_func_559(insn_t insn, reg_t reg); -reg_t insn_func_562(insn_t insn, reg_t reg); -reg_t insn_func_563(insn_t insn, reg_t reg); -reg_t insn_func_569(insn_t insn, reg_t reg); -reg_t insn_func_570(insn_t insn, reg_t reg); -reg_t insn_func_571(insn_t insn, reg_t reg); -reg_t insn_func_578(insn_t insn, reg_t reg); -reg_t insn_func_594(insn_t insn, reg_t reg); -reg_t insn_func_595(insn_t insn, reg_t reg); -reg_t insn_func_601(insn_t insn, reg_t reg); -reg_t insn_func_602(insn_t insn, reg_t reg); -reg_t insn_func_610(insn_t insn, reg_t reg); -reg_t insn_func_611(insn_t insn, reg_t reg); -reg_t insn_func_619(insn_t insn, reg_t reg); -reg_t insn_func_626(insn_t insn, reg_t reg); -reg_t insn_func_631(insn_t insn, reg_t reg); -reg_t insn_func_633(insn_t insn, reg_t reg); -reg_t insn_func_634(insn_t insn, reg_t reg); -reg_t insn_func_635(insn_t insn, reg_t reg); -reg_t insn_func_642(insn_t insn, reg_t reg); -reg_t insn_func_643(insn_t insn, reg_t reg); -reg_t insn_func_651(insn_t insn, reg_t reg); -reg_t insn_func_658(insn_t insn, reg_t reg); -reg_t insn_func_659(insn_t insn, reg_t reg); -reg_t insn_func_665(insn_t insn, reg_t reg); -reg_t insn_func_666(insn_t insn, reg_t reg); -reg_t insn_func_667(insn_t insn, reg_t reg); -reg_t insn_func_674(insn_t insn, reg_t reg); -reg_t insn_func_687(insn_t insn, reg_t reg); -reg_t insn_func_690(insn_t insn, reg_t reg); -reg_t insn_func_691(insn_t insn, reg_t reg); -reg_t insn_func_697(insn_t insn, reg_t reg); -reg_t insn_func_698(insn_t insn, reg_t reg); -reg_t insn_func_699(insn_t insn, reg_t reg); -reg_t insn_func_706(insn_t insn, reg_t reg); -reg_t insn_func_722(insn_t insn, reg_t reg); -reg_t insn_func_723(insn_t insn, reg_t reg); -reg_t insn_func_729(insn_t insn, reg_t reg); -reg_t insn_func_730(insn_t insn, reg_t reg); -reg_t insn_func_738(insn_t insn, reg_t reg); -reg_t insn_func_739(insn_t insn, reg_t reg); -reg_t insn_func_754(insn_t insn, reg_t reg); -reg_t insn_func_755(insn_t insn, reg_t reg); -reg_t insn_func_759(insn_t insn, reg_t reg); -reg_t insn_func_761(insn_t insn, reg_t reg); -reg_t insn_func_762(insn_t insn, reg_t reg); -reg_t insn_func_763(insn_t insn, reg_t reg); -reg_t insn_func_770(insn_t insn, reg_t reg); -reg_t insn_func_771(insn_t insn, reg_t reg); -reg_t insn_func_779(insn_t insn, reg_t reg); -reg_t insn_func_786(insn_t insn, reg_t reg); -reg_t insn_func_787(insn_t insn, reg_t reg); -reg_t insn_func_793(insn_t insn, reg_t reg); -reg_t insn_func_794(insn_t insn, reg_t reg); -reg_t insn_func_796(insn_t insn, reg_t reg); -reg_t insn_func_802(insn_t insn, reg_t reg); -reg_t insn_func_815(insn_t insn, reg_t reg); -reg_t insn_func_818(insn_t insn, reg_t reg); -reg_t insn_func_819(insn_t insn, reg_t reg); -reg_t insn_func_825(insn_t insn, reg_t reg); -reg_t insn_func_826(insn_t insn, reg_t reg); -reg_t insn_func_827(insn_t insn, reg_t reg); -reg_t insn_func_834(insn_t insn, reg_t reg); -reg_t insn_func_850(insn_t insn, reg_t reg); -reg_t insn_func_857(insn_t insn, reg_t reg); -reg_t insn_func_858(insn_t insn, reg_t reg); -reg_t insn_func_866(insn_t insn, reg_t reg); -reg_t insn_func_867(insn_t insn, reg_t reg); -reg_t insn_func_882(insn_t insn, reg_t reg); -reg_t insn_func_889(insn_t insn, reg_t reg); -reg_t insn_func_890(insn_t insn, reg_t reg); -reg_t insn_func_898(insn_t insn, reg_t reg); -reg_t insn_func_914(insn_t insn, reg_t reg); -reg_t insn_func_915(insn_t insn, reg_t reg); -reg_t insn_func_921(insn_t insn, reg_t reg); -reg_t insn_func_922(insn_t insn, reg_t reg); -reg_t insn_func_930(insn_t insn, reg_t reg); -reg_t insn_func_943(insn_t insn, reg_t reg); -reg_t insn_func_946(insn_t insn, reg_t reg); -reg_t insn_func_947(insn_t insn, reg_t reg); -reg_t insn_func_953(insn_t insn, reg_t reg); -reg_t insn_func_954(insn_t insn, reg_t reg); -reg_t insn_func_955(insn_t insn, reg_t reg); -reg_t insn_func_962(insn_t insn, reg_t reg); -reg_t insn_func_978(insn_t insn, reg_t reg); -reg_t insn_func_985(insn_t insn, reg_t reg); -reg_t insn_func_986(insn_t insn, reg_t reg); -reg_t insn_func_994(insn_t insn, reg_t reg); -reg_t insn_func_995(insn_t insn, reg_t reg); -reg_t insn_func_1010(insn_t insn, reg_t reg); -reg_t insn_func_1011(insn_t insn, reg_t reg); -reg_t insn_func_1017(insn_t insn, reg_t reg); -reg_t insn_func_1018(insn_t insn, reg_t reg); diff --git a/riscv/icsim.cc b/riscv/icsim.cc deleted file mode 100644 index 308e7ed..0000000 --- a/riscv/icsim.cc +++ /dev/null @@ -1,100 +0,0 @@ -#include "icsim.h" -#include <stdexcept> -#include <iostream> -#include <iomanip> - -icsim_t::icsim_t(size_t _sets, size_t _ways, size_t _linesz, const char* _name) - : sets(_sets), ways(_ways), linesz(_linesz), idx_mask(_sets-1), name(_name) -{ - if(sets == 0 || (sets & (sets-1))) - throw std::logic_error("sets not a power of 2"); - if(linesz == 0 || (linesz & (linesz-1))) - throw std::logic_error("linesz not a power of 2"); - - idx_shift = 0; - while(_linesz >>= 1) - idx_shift++; - - tags = new uint64_t[sets*ways]; - memset(tags, 0, sets*ways*sizeof(uint64_t)); - - read_accesses = 0; - read_misses = 0; - bytes_read = 0; - write_accesses = 0; - write_misses = 0; - bytes_written = 0; - writebacks = 0; -} - -icsim_t::icsim_t(const icsim_t& rhs) - : sets(rhs.sets), ways(rhs.ways), linesz(rhs.linesz), - idx_shift(rhs.idx_shift), idx_mask(rhs.idx_mask), name(rhs.name) -{ - tags = new uint64_t[sets*ways]; - memcpy(tags, rhs.tags, sets*ways*sizeof(uint64_t)); -} - -icsim_t::~icsim_t() -{ - delete [] tags; -} - -void icsim_t::print_stats() -{ - if(read_accesses + write_accesses == 0) - return; - - float mr = 100.0f*(read_misses+write_misses)/(read_accesses+write_accesses); - - std::cout << std::setprecision(3) << std::fixed; - std::cout << name << " "; - std::cout << "Bytes Read: " << bytes_read << std::endl; - std::cout << name << " "; - std::cout << "Bytes Written: " << bytes_written << std::endl; - std::cout << name << " "; - std::cout << "Read Accesses: " << read_accesses << std::endl; - std::cout << name << " "; - std::cout << "Write Accesses: " << write_accesses << std::endl; - std::cout << name << " "; - std::cout << "Read Misses: " << read_misses << std::endl; - std::cout << name << " "; - std::cout << "Write Misses: " << write_misses << std::endl; - std::cout << name << " "; - std::cout << "Writebacks: " << writebacks << std::endl; - std::cout << name << " "; - std::cout << "Miss Rate: " << mr << '%' << std::endl; - - float cr = read_accesses == 0 ? 0.0f : 100.0f*bytes_read/(4*read_accesses); - if(name == "I$") - { - std::cout << name << " "; - std::cout << "RVC compression ratio: " << cr << '%' << std::endl; - } -} - -void icsim_t::tick(uint64_t pc, int insnlen, bool store) -{ - store ? write_accesses++ : read_accesses++; - (store ? bytes_written : bytes_read) += insnlen; - - size_t idx = (pc >> idx_shift) & idx_mask; - size_t tag = (pc >> idx_shift) | VALID; - - for(size_t i = 0; i < ways; i++) - { - if(tag == (tags[idx + i*sets] & ~DIRTY)) // hit - { - if(store) - tags[idx + i*sets] |= DIRTY; - return; - } - } - - store ? write_misses++ : read_misses++; - - size_t way = lfsr.next() % ways; - if((tags[idx + way*sets] & (VALID | DIRTY)) == (VALID | DIRTY)) - writebacks++; - tags[idx + way*sets] = tag; -} diff --git a/riscv/icsim.h b/riscv/icsim.h deleted file mode 100644 index 48931f5..0000000 --- a/riscv/icsim.h +++ /dev/null @@ -1,52 +0,0 @@ -#ifndef _RISCV_ICSIM_H -#define _RISCV_ICSIM_H - -#include <cstring> -#include <string> -#include <stdint.h> - -class lfsr_t -{ -public: - lfsr_t() : reg(1) {} - lfsr_t(const lfsr_t& lfsr) : reg(lfsr.reg) {} - uint32_t next() { return reg = (reg>>1)^(-(reg&1) & 0xd0000001); } -private: - uint32_t reg; -}; - -class icsim_t -{ -public: - icsim_t(size_t sets, size_t ways, size_t linesz, const char* name); - icsim_t(const icsim_t& rhs); - ~icsim_t(); - - void tick(uint64_t pc, int insnlen, bool store); - void print_stats(); -private: - lfsr_t lfsr; - - size_t sets; - size_t ways; - size_t linesz; - size_t idx_shift; - size_t idx_mask; - - uint64_t* tags; - - uint64_t read_accesses; - uint64_t read_misses; - uint64_t bytes_read; - uint64_t write_accesses; - uint64_t write_misses; - uint64_t bytes_written; - uint64_t writebacks; - - std::string name; - - static const uint64_t VALID = 1ULL << 63; - static const uint64_t DIRTY = 1ULL << 62; -}; - -#endif diff --git a/riscv/insn_footer.h b/riscv/insn_footer.h deleted file mode 100644 index 0d53966..0000000 --- a/riscv/insn_footer.h +++ /dev/null @@ -1,2 +0,0 @@ - return npc; -} diff --git a/riscv/insn_header.h b/riscv/insn_header.h deleted file mode 100644 index 9496572..0000000 --- a/riscv/insn_header.h +++ /dev/null @@ -1,7 +0,0 @@ -#include "processor.h" -#include "common.h" -#include "config.h" -#include "sim.h" -#include "softfloat.h" -#include "platform.h" // softfloat isNaNF32UI, etc. -#include "internals.h" // ditto diff --git a/riscv/insns/add.h b/riscv/insns/add.h deleted file mode 100644 index 34d49ff..0000000 --- a/riscv/insns/add.h +++ /dev/null @@ -1 +0,0 @@ -RD = sext_xprlen(RS1 + RS2); diff --git a/riscv/insns/addi.h b/riscv/insns/addi.h deleted file mode 100644 index 88881e5..0000000 --- a/riscv/insns/addi.h +++ /dev/null @@ -1 +0,0 @@ -RD = sext_xprlen(RS1 + SIMM); diff --git a/riscv/insns/addiw.h b/riscv/insns/addiw.h deleted file mode 100644 index 23ae278..0000000 --- a/riscv/insns/addiw.h +++ /dev/null @@ -1,2 +0,0 @@ -require_xpr64; -RD = sext32(SIMM + RS1); diff --git a/riscv/insns/addw.h b/riscv/insns/addw.h deleted file mode 100644 index 4e2ed56..0000000 --- a/riscv/insns/addw.h +++ /dev/null @@ -1,2 +0,0 @@ -require_xpr64; -RD = sext32(RS1 + RS2); diff --git a/riscv/insns/amoadd_d.h b/riscv/insns/amoadd_d.h deleted file mode 100644 index b8450bf..0000000 --- a/riscv/insns/amoadd_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_xpr64; -reg_t v = mmu.load_uint64(RS1); -mmu.store_uint64(RS1, RS2 + v); -RD = v; diff --git a/riscv/insns/amoadd_w.h b/riscv/insns/amoadd_w.h deleted file mode 100644 index 033b3c8..0000000 --- a/riscv/insns/amoadd_w.h +++ /dev/null @@ -1,3 +0,0 @@ -reg_t v = mmu.load_int32(RS1); -mmu.store_uint32(RS1, RS2 + v); -RD = v; diff --git a/riscv/insns/amoand_d.h b/riscv/insns/amoand_d.h deleted file mode 100644 index 586eb7f..0000000 --- a/riscv/insns/amoand_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_xpr64; -reg_t v = mmu.load_uint64(RS1); -mmu.store_uint64(RS1, RS2 & v); -RD = v; diff --git a/riscv/insns/amoand_w.h b/riscv/insns/amoand_w.h deleted file mode 100644 index 18a9249..0000000 --- a/riscv/insns/amoand_w.h +++ /dev/null @@ -1,3 +0,0 @@ -reg_t v = mmu.load_int32(RS1); -mmu.store_uint32(RS1, RS2 & v); -RD = v; diff --git a/riscv/insns/amomax_d.h b/riscv/insns/amomax_d.h deleted file mode 100644 index 1a0bc8a..0000000 --- a/riscv/insns/amomax_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_xpr64; -sreg_t v = mmu.load_int64(RS1); -mmu.store_uint64(RS1, std::max(sreg_t(RS2),v)); -RD = v; diff --git a/riscv/insns/amomax_w.h b/riscv/insns/amomax_w.h deleted file mode 100644 index ff9c2da..0000000 --- a/riscv/insns/amomax_w.h +++ /dev/null @@ -1,3 +0,0 @@ -int32_t v = mmu.load_int32(RS1); -mmu.store_uint32(RS1, std::max(int32_t(RS2),v)); -RD = v; diff --git a/riscv/insns/amomaxu_d.h b/riscv/insns/amomaxu_d.h deleted file mode 100644 index ccfaf1d..0000000 --- a/riscv/insns/amomaxu_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_xpr64; -reg_t v = mmu.load_uint64(RS1); -mmu.store_uint64(RS1, std::max(RS2,v)); -RD = v; diff --git a/riscv/insns/amomaxu_w.h b/riscv/insns/amomaxu_w.h deleted file mode 100644 index 075847d..0000000 --- a/riscv/insns/amomaxu_w.h +++ /dev/null @@ -1,3 +0,0 @@ -uint32_t v = mmu.load_int32(RS1); -mmu.store_uint32(RS1, std::max(uint32_t(RS2),v)); -RD = (int32_t)v; diff --git a/riscv/insns/amomin_d.h b/riscv/insns/amomin_d.h deleted file mode 100644 index 4f3b6d6..0000000 --- a/riscv/insns/amomin_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_xpr64; -sreg_t v = mmu.load_int64(RS1); -mmu.store_uint64(RS1, std::min(sreg_t(RS2),v)); -RD = v; diff --git a/riscv/insns/amomin_w.h b/riscv/insns/amomin_w.h deleted file mode 100644 index 529ad50..0000000 --- a/riscv/insns/amomin_w.h +++ /dev/null @@ -1,3 +0,0 @@ -int32_t v = mmu.load_int32(RS1); -mmu.store_uint32(RS1, std::min(int32_t(RS2),v)); -RD = v; diff --git a/riscv/insns/amominu_d.h b/riscv/insns/amominu_d.h deleted file mode 100644 index c09c51a..0000000 --- a/riscv/insns/amominu_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_xpr64; -reg_t v = mmu.load_uint64(RS1); -mmu.store_uint64(RS1, std::min(RS2,v)); -RD = v; diff --git a/riscv/insns/amominu_w.h b/riscv/insns/amominu_w.h deleted file mode 100644 index d8d6377..0000000 --- a/riscv/insns/amominu_w.h +++ /dev/null @@ -1,3 +0,0 @@ -uint32_t v = mmu.load_int32(RS1); -mmu.store_uint32(RS1, std::min(uint32_t(RS2),v)); -RD = (int32_t)v; diff --git a/riscv/insns/amoor_d.h b/riscv/insns/amoor_d.h deleted file mode 100644 index 76a4508..0000000 --- a/riscv/insns/amoor_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_xpr64; -reg_t v = mmu.load_uint64(RS1); -mmu.store_uint64(RS1, RS2 | v); -RD = v; diff --git a/riscv/insns/amoor_w.h b/riscv/insns/amoor_w.h deleted file mode 100644 index 741fbef..0000000 --- a/riscv/insns/amoor_w.h +++ /dev/null @@ -1,3 +0,0 @@ -reg_t v = mmu.load_int32(RS1); -mmu.store_uint32(RS1, RS2 | v); -RD = v; diff --git a/riscv/insns/amoswap_d.h b/riscv/insns/amoswap_d.h deleted file mode 100644 index 43e3538..0000000 --- a/riscv/insns/amoswap_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_xpr64; -reg_t v = mmu.load_uint64(RS1); -mmu.store_uint64(RS1, RS2); -RD = v; diff --git a/riscv/insns/amoswap_w.h b/riscv/insns/amoswap_w.h deleted file mode 100644 index 30e6102..0000000 --- a/riscv/insns/amoswap_w.h +++ /dev/null @@ -1,3 +0,0 @@ -reg_t v = mmu.load_int32(RS1); -mmu.store_uint32(RS1, RS2); -RD = v; diff --git a/riscv/insns/and.h b/riscv/insns/and.h deleted file mode 100644 index 88ac1d8..0000000 --- a/riscv/insns/and.h +++ /dev/null @@ -1 +0,0 @@ -RD = RS1 & RS2; diff --git a/riscv/insns/andi.h b/riscv/insns/andi.h deleted file mode 100644 index 5caea16..0000000 --- a/riscv/insns/andi.h +++ /dev/null @@ -1 +0,0 @@ -RD = SIMM & RS1; diff --git a/riscv/insns/beq.h b/riscv/insns/beq.h deleted file mode 100644 index 7b26488..0000000 --- a/riscv/insns/beq.h +++ /dev/null @@ -1,2 +0,0 @@ -if(cmp_trunc(RS1) == cmp_trunc(RS2)) - set_pc(BRANCH_TARGET); diff --git a/riscv/insns/bge.h b/riscv/insns/bge.h deleted file mode 100644 index dca544b..0000000 --- a/riscv/insns/bge.h +++ /dev/null @@ -1,2 +0,0 @@ -if(sreg_t(cmp_trunc(RS1)) >= sreg_t(cmp_trunc(RS2))) - set_pc(BRANCH_TARGET); diff --git a/riscv/insns/bgeu.h b/riscv/insns/bgeu.h deleted file mode 100644 index 6325466..0000000 --- a/riscv/insns/bgeu.h +++ /dev/null @@ -1,2 +0,0 @@ -if(cmp_trunc(RS1) >= cmp_trunc(RS2)) - set_pc(BRANCH_TARGET); diff --git a/riscv/insns/blt.h b/riscv/insns/blt.h deleted file mode 100644 index d84fd7a..0000000 --- a/riscv/insns/blt.h +++ /dev/null @@ -1,2 +0,0 @@ -if(sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2))) - set_pc(BRANCH_TARGET); diff --git a/riscv/insns/bltu.h b/riscv/insns/bltu.h deleted file mode 100644 index 250fd4f..0000000 --- a/riscv/insns/bltu.h +++ /dev/null @@ -1,2 +0,0 @@ -if(cmp_trunc(RS1) < cmp_trunc(RS2)) - set_pc(BRANCH_TARGET); diff --git a/riscv/insns/bne.h b/riscv/insns/bne.h deleted file mode 100644 index f775721..0000000 --- a/riscv/insns/bne.h +++ /dev/null @@ -1,2 +0,0 @@ -if(cmp_trunc(RS1) != cmp_trunc(RS2)) - set_pc(BRANCH_TARGET); diff --git a/riscv/insns/break.h b/riscv/insns/break.h deleted file mode 100644 index 7fd3d66..0000000 --- a/riscv/insns/break.h +++ /dev/null @@ -1 +0,0 @@ -throw trap_breakpoint; diff --git a/riscv/insns/c_add.h b/riscv/insns/c_add.h deleted file mode 100644 index 2170d69..0000000 --- a/riscv/insns/c_add.h +++ /dev/null @@ -1,2 +0,0 @@ -require_rvc; -CRD = CRS1 + CRS2; diff --git a/riscv/insns/c_add3.h b/riscv/insns/c_add3.h deleted file mode 100644 index 914c85d..0000000 --- a/riscv/insns/c_add3.h +++ /dev/null @@ -1,2 +0,0 @@ -require_rvc; -CRDS = CRS1S + CRS2BS; diff --git a/riscv/insns/c_addi.h b/riscv/insns/c_addi.h deleted file mode 100644 index 448e31a..0000000 --- a/riscv/insns/c_addi.h +++ /dev/null @@ -1,10 +0,0 @@ -require_rvc; -if(CRD_REGNUM == 0) -{ - reg_t temp = CRS1; - if(CIMM6 & 0x20) - RA = npc; - set_pc(temp); -} -else - CRD = sext_xprlen(CRS2 + CIMM6); diff --git a/riscv/insns/c_addiw.h b/riscv/insns/c_addiw.h deleted file mode 100644 index 6a1e0a3..0000000 --- a/riscv/insns/c_addiw.h +++ /dev/null @@ -1,3 +0,0 @@ -require_rvc; -require_xpr64; -CRD = sext32(CRS2 + CIMM6); diff --git a/riscv/insns/c_and3.h b/riscv/insns/c_and3.h deleted file mode 100644 index b506d6a..0000000 --- a/riscv/insns/c_and3.h +++ /dev/null @@ -1,2 +0,0 @@ -require_rvc; -CRDS = CRS1S & CRS2BS; diff --git a/riscv/insns/c_beq.h b/riscv/insns/c_beq.h deleted file mode 100644 index 031d96d..0000000 --- a/riscv/insns/c_beq.h +++ /dev/null @@ -1,3 +0,0 @@ -require_rvc; -if(cmp_trunc(CRS1S) == cmp_trunc(CRS2S)) - set_pc(CBRANCH_TARGET); diff --git a/riscv/insns/c_bne.h b/riscv/insns/c_bne.h deleted file mode 100644 index caf9229..0000000 --- a/riscv/insns/c_bne.h +++ /dev/null @@ -1,3 +0,0 @@ -require_rvc; -if(cmp_trunc(CRS1S) != cmp_trunc(CRS2S)) - set_pc(CBRANCH_TARGET); diff --git a/riscv/insns/c_fld.h b/riscv/insns/c_fld.h deleted file mode 100644 index a726039..0000000 --- a/riscv/insns/c_fld.h +++ /dev/null @@ -1,3 +0,0 @@ -require_rvc; -require_fp; -FCRDS = mmu.load_int64(CRS1S+CIMM5*8); diff --git a/riscv/insns/c_flw.h b/riscv/insns/c_flw.h deleted file mode 100644 index cdb7221..0000000 --- a/riscv/insns/c_flw.h +++ /dev/null @@ -1,3 +0,0 @@ -require_rvc; -require_fp; -FCRDS = mmu.load_int32(CRS1S+CIMM5*4); diff --git a/riscv/insns/c_fsd.h b/riscv/insns/c_fsd.h deleted file mode 100644 index 20814fd..0000000 --- a/riscv/insns/c_fsd.h +++ /dev/null @@ -1,3 +0,0 @@ -require_rvc; -require_fp; -mmu.store_uint64(CRS1S+CIMM5*8, FCRS2S); diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h deleted file mode 100644 index 1d21629..0000000 --- a/riscv/insns/c_fsw.h +++ /dev/null @@ -1,3 +0,0 @@ -require_rvc; -require_fp; -mmu.store_uint32(CRS1S+CIMM5*4, FCRS2S); diff --git a/riscv/insns/c_j.h b/riscv/insns/c_j.h deleted file mode 100644 index 5ba9c73..0000000 --- a/riscv/insns/c_j.h +++ /dev/null @@ -1,2 +0,0 @@ -require_rvc; -set_pc(CJUMP_TARGET); diff --git a/riscv/insns/c_ld.h b/riscv/insns/c_ld.h deleted file mode 100644 index f9c07af..0000000 --- a/riscv/insns/c_ld.h +++ /dev/null @@ -1,3 +0,0 @@ -require_rvc; -require_xpr64; -CRDS = mmu.load_int64(CRS1S+CIMM5*8); diff --git a/riscv/insns/c_ld0.h b/riscv/insns/c_ld0.h deleted file mode 100644 index f51a966..0000000 --- a/riscv/insns/c_ld0.h +++ /dev/null @@ -1,3 +0,0 @@ -require_rvc; -require_xpr64; -CRD = mmu.load_int64(CRS1); diff --git a/riscv/insns/c_ldsp.h b/riscv/insns/c_ldsp.h deleted file mode 100644 index 1fbd9bd..0000000 --- a/riscv/insns/c_ldsp.h +++ /dev/null @@ -1,3 +0,0 @@ -require_rvc; -require_xpr64; -CRD = mmu.load_int64(XPR[30]+CIMM6*8); diff --git a/riscv/insns/c_li.h b/riscv/insns/c_li.h deleted file mode 100644 index e65614e..0000000 --- a/riscv/insns/c_li.h +++ /dev/null @@ -1,2 +0,0 @@ -require_rvc; -CRD = CIMM6; diff --git a/riscv/insns/c_lw.h b/riscv/insns/c_lw.h deleted file mode 100644 index 4796ab8..0000000 --- a/riscv/insns/c_lw.h +++ /dev/null @@ -1,2 +0,0 @@ -require_rvc; -CRDS = mmu.load_int32(CRS1S+CIMM5*4); diff --git a/riscv/insns/c_lw0.h b/riscv/insns/c_lw0.h deleted file mode 100644 index d263a80..0000000 --- a/riscv/insns/c_lw0.h +++ /dev/null @@ -1,2 +0,0 @@ -require_rvc; -CRD = mmu.load_int32(CRS1); diff --git a/riscv/insns/c_lwsp.h b/riscv/insns/c_lwsp.h deleted file mode 100644 index 318342a..0000000 --- a/riscv/insns/c_lwsp.h +++ /dev/null @@ -1,2 +0,0 @@ -require_rvc; -CRD = mmu.load_int32(XPR[30]+CIMM6*4); diff --git a/riscv/insns/c_move.h b/riscv/insns/c_move.h deleted file mode 100644 index b0aef33..0000000 --- a/riscv/insns/c_move.h +++ /dev/null @@ -1,2 +0,0 @@ -require_rvc; -CRD = CRS1; diff --git a/riscv/insns/c_or3.h b/riscv/insns/c_or3.h deleted file mode 100644 index 143e2ae..0000000 --- a/riscv/insns/c_or3.h +++ /dev/null @@ -1,2 +0,0 @@ -require_rvc; -CRDS = CRS1S | CRS2BS; diff --git a/riscv/insns/c_sd.h b/riscv/insns/c_sd.h deleted file mode 100644 index b2eb456..0000000 --- a/riscv/insns/c_sd.h +++ /dev/null @@ -1,3 +0,0 @@ -require_rvc; -require_xpr64; -mmu.store_uint64(CRS1S+CIMM5*8, CRS2S); diff --git a/riscv/insns/c_sdsp.h b/riscv/insns/c_sdsp.h deleted file mode 100644 index ca97d51..0000000 --- a/riscv/insns/c_sdsp.h +++ /dev/null @@ -1,3 +0,0 @@ -require_rvc; -require_xpr64; -mmu.store_uint64(XPR[30]+CIMM6*8, CRS2); diff --git a/riscv/insns/c_slli.h b/riscv/insns/c_slli.h deleted file mode 100644 index 5026767..0000000 --- a/riscv/insns/c_slli.h +++ /dev/null @@ -1,5 +0,0 @@ -require_rvc; -if(xpr64) - CRDS = CRDS << CIMM5U; -else - CRDS = sext32(CRDS << CIMM5U); diff --git a/riscv/insns/c_slli32.h b/riscv/insns/c_slli32.h deleted file mode 100644 index 1e3e958..0000000 --- a/riscv/insns/c_slli32.h +++ /dev/null @@ -1,3 +0,0 @@ -require_rvc; -require_xpr64; -CRDS = CRDS << (32+CIMM5U); diff --git a/riscv/insns/c_slliw.h b/riscv/insns/c_slliw.h deleted file mode 100644 index 9e428f5..0000000 --- a/riscv/insns/c_slliw.h +++ /dev/null @@ -1,3 +0,0 @@ -require_rvc; -require_xpr64; -CRDS = sext32(CRDS << CIMM5U); diff --git a/riscv/insns/c_srai.h b/riscv/insns/c_srai.h deleted file mode 100644 index aa33424..0000000 --- a/riscv/insns/c_srai.h +++ /dev/null @@ -1,5 +0,0 @@ -require_rvc; -if(xpr64) - CRDS = sreg_t(CRDS) >> CIMM5U; -else - CRDS = sext32(int32_t(CRDS) >> CIMM5U); diff --git a/riscv/insns/c_srai32.h b/riscv/insns/c_srai32.h deleted file mode 100644 index ca7b024..0000000 --- a/riscv/insns/c_srai32.h +++ /dev/null @@ -1,3 +0,0 @@ -require_rvc; -require_xpr64; -CRDS = sreg_t(CRDS) >> (32+CIMM5U); diff --git a/riscv/insns/c_srli.h b/riscv/insns/c_srli.h deleted file mode 100644 index 56e0681..0000000 --- a/riscv/insns/c_srli.h +++ /dev/null @@ -1,5 +0,0 @@ -require_rvc; -if(xpr64) - CRDS = CRDS >> CIMM5U; -else - CRDS = sext32(uint32_t(CRDS) >> CIMM5U); diff --git a/riscv/insns/c_srli32.h b/riscv/insns/c_srli32.h deleted file mode 100644 index 4f5b8ea..0000000 --- a/riscv/insns/c_srli32.h +++ /dev/null @@ -1,3 +0,0 @@ -require_rvc; -require_xpr64; -CRDS = CRDS >> (32+CIMM5U); diff --git a/riscv/insns/c_sub.h b/riscv/insns/c_sub.h deleted file mode 100644 index 9fd8932..0000000 --- a/riscv/insns/c_sub.h +++ /dev/null @@ -1,2 +0,0 @@ -require_rvc; -CRD = CRS1 - CRS2; diff --git a/riscv/insns/c_sub3.h b/riscv/insns/c_sub3.h deleted file mode 100644 index 53afc84..0000000 --- a/riscv/insns/c_sub3.h +++ /dev/null @@ -1,2 +0,0 @@ -require_rvc; -CRDS = CRS1S - CRS2BS; diff --git a/riscv/insns/c_sw.h b/riscv/insns/c_sw.h deleted file mode 100644 index f604adf..0000000 --- a/riscv/insns/c_sw.h +++ /dev/null @@ -1,2 +0,0 @@ -require_rvc; -mmu.store_uint32(CRS1S+CIMM5*4, CRS2S); diff --git a/riscv/insns/c_swsp.h b/riscv/insns/c_swsp.h deleted file mode 100644 index 0508f12..0000000 --- a/riscv/insns/c_swsp.h +++ /dev/null @@ -1,2 +0,0 @@ -require_rvc; -mmu.store_uint32(XPR[30]+CIMM6*4, CRS2); diff --git a/riscv/insns/cflush.h b/riscv/insns/cflush.h deleted file mode 100644 index 5117ca0..0000000 --- a/riscv/insns/cflush.h +++ /dev/null @@ -1 +0,0 @@ -require_supervisor; diff --git a/riscv/insns/di.h b/riscv/insns/di.h deleted file mode 100644 index 31280d5..0000000 --- a/riscv/insns/di.h +++ /dev/null @@ -1,4 +0,0 @@ -require_supervisor; -uint32_t temp = sr; -set_sr(sr & ~SR_ET); -RD = temp; diff --git a/riscv/insns/div.h b/riscv/insns/div.h deleted file mode 100644 index 82a4066..0000000 --- a/riscv/insns/div.h +++ /dev/null @@ -1,6 +0,0 @@ -if(RS2 == 0) - RD = UINT64_MAX; -else if(sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1) - RD = RS1; -else - RD = sext_xprlen(sext_xprlen(RS1) / sext_xprlen(RS2)); diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h deleted file mode 100644 index 681afd2..0000000 --- a/riscv/insns/divu.h +++ /dev/null @@ -1,4 +0,0 @@ -if(RS2 == 0) - RD = UINT64_MAX; -else - RD = sext_xprlen(zext_xprlen(RS1) / zext_xprlen(RS2)); diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h deleted file mode 100644 index 0ceb040..0000000 --- a/riscv/insns/divuw.h +++ /dev/null @@ -1,5 +0,0 @@ -require_xpr64; -if(RS2 == 0) - RD = UINT64_MAX; -else - RD = sext32(zext32(RS1) / zext32(RS2)); diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h deleted file mode 100644 index 51c3d80..0000000 --- a/riscv/insns/divw.h +++ /dev/null @@ -1,7 +0,0 @@ -require_xpr64; -if(RS2 == 0) - RD = UINT64_MAX; -else if(int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1) - RD = RS1; -else - RD = sext32(int32_t(RS1) / int32_t(RS2)); diff --git a/riscv/insns/ei.h b/riscv/insns/ei.h deleted file mode 100644 index 8306aeb..0000000 --- a/riscv/insns/ei.h +++ /dev/null @@ -1,4 +0,0 @@ -require_supervisor; -uint32_t temp = sr; -set_sr(sr | SR_ET); -RD = temp; diff --git a/riscv/insns/eret.h b/riscv/insns/eret.h deleted file mode 100644 index 46d5bed..0000000 --- a/riscv/insns/eret.h +++ /dev/null @@ -1,5 +0,0 @@ -require_supervisor; -if(sr & SR_ET) - throw trap_illegal_instruction; -set_sr(((sr & SR_PS) ? sr : (sr & ~SR_S)) | SR_ET); -set_pc(epc); diff --git a/riscv/insns/fadd_d.h b/riscv/insns/fadd_d.h deleted file mode 100644 index 48c76a7..0000000 --- a/riscv/insns/fadd_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = f64_add(FRS1, FRS2); -set_fp_exceptions; diff --git a/riscv/insns/fadd_s.h b/riscv/insns/fadd_s.h deleted file mode 100644 index 2fd5429..0000000 --- a/riscv/insns/fadd_s.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = f32_add(FRS1, FRS2); -set_fp_exceptions; diff --git a/riscv/insns/fcvt_d_l.h b/riscv/insns/fcvt_d_l.h deleted file mode 100644 index 68c0482..0000000 --- a/riscv/insns/fcvt_d_l.h +++ /dev/null @@ -1,5 +0,0 @@ -require_xpr64; -require_fp; -softfloat_roundingMode = RM; -FRD = i64_to_f64(RS1); -set_fp_exceptions; diff --git a/riscv/insns/fcvt_d_lu.h b/riscv/insns/fcvt_d_lu.h deleted file mode 100644 index 2032758..0000000 --- a/riscv/insns/fcvt_d_lu.h +++ /dev/null @@ -1,5 +0,0 @@ -require_xpr64; -require_fp; -softfloat_roundingMode = RM; -FRD = ui64_to_f64(RS1); -set_fp_exceptions; diff --git a/riscv/insns/fcvt_d_s.h b/riscv/insns/fcvt_d_s.h deleted file mode 100644 index 6b1a09c..0000000 --- a/riscv/insns/fcvt_d_s.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = f32_to_f64(FRS1); -set_fp_exceptions; diff --git a/riscv/insns/fcvt_d_w.h b/riscv/insns/fcvt_d_w.h deleted file mode 100644 index 52abd75..0000000 --- a/riscv/insns/fcvt_d_w.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = i32_to_f64((int32_t)RS1); -set_fp_exceptions; diff --git a/riscv/insns/fcvt_d_wu.h b/riscv/insns/fcvt_d_wu.h deleted file mode 100644 index 61a8a78..0000000 --- a/riscv/insns/fcvt_d_wu.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = ui32_to_f64((uint32_t)RS1); -set_fp_exceptions; diff --git a/riscv/insns/fcvt_l_d.h b/riscv/insns/fcvt_l_d.h deleted file mode 100644 index 206ba4f..0000000 --- a/riscv/insns/fcvt_l_d.h +++ /dev/null @@ -1,5 +0,0 @@ -require_xpr64; -require_fp; -softfloat_roundingMode = RM; -RD = f64_to_i64(FRS1, RM, true); -set_fp_exceptions; diff --git a/riscv/insns/fcvt_l_s.h b/riscv/insns/fcvt_l_s.h deleted file mode 100644 index e05f476..0000000 --- a/riscv/insns/fcvt_l_s.h +++ /dev/null @@ -1,5 +0,0 @@ -require_xpr64; -require_fp; -softfloat_roundingMode = RM; -RD = f32_to_i64(FRS1, RM, true); -set_fp_exceptions; diff --git a/riscv/insns/fcvt_lu_d.h b/riscv/insns/fcvt_lu_d.h deleted file mode 100644 index 44c3dd6..0000000 --- a/riscv/insns/fcvt_lu_d.h +++ /dev/null @@ -1,5 +0,0 @@ -require_xpr64; -require_fp; -softfloat_roundingMode = RM; -RD = f64_to_ui64(FRS1, RM, true); -set_fp_exceptions; diff --git a/riscv/insns/fcvt_lu_s.h b/riscv/insns/fcvt_lu_s.h deleted file mode 100644 index 13de436..0000000 --- a/riscv/insns/fcvt_lu_s.h +++ /dev/null @@ -1,5 +0,0 @@ -require_xpr64; -require_fp; -softfloat_roundingMode = RM; -RD = f32_to_ui64(FRS1, RM, true); -set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_d.h b/riscv/insns/fcvt_s_d.h deleted file mode 100644 index e5289c4..0000000 --- a/riscv/insns/fcvt_s_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = f64_to_f32(FRS1); -set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_l.h b/riscv/insns/fcvt_s_l.h deleted file mode 100644 index f149229..0000000 --- a/riscv/insns/fcvt_s_l.h +++ /dev/null @@ -1,5 +0,0 @@ -require_xpr64; -require_fp; -softfloat_roundingMode = RM; -FRD = i64_to_f32(RS1); -set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_lu.h b/riscv/insns/fcvt_s_lu.h deleted file mode 100644 index d9d0946..0000000 --- a/riscv/insns/fcvt_s_lu.h +++ /dev/null @@ -1,5 +0,0 @@ -require_xpr64; -require_fp; -softfloat_roundingMode = RM; -FRD = ui64_to_f32(RS1); -set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_w.h b/riscv/insns/fcvt_s_w.h deleted file mode 100644 index dedebb5..0000000 --- a/riscv/insns/fcvt_s_w.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = i32_to_f32((int32_t)RS1); -set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_wu.h b/riscv/insns/fcvt_s_wu.h deleted file mode 100644 index abb782c..0000000 --- a/riscv/insns/fcvt_s_wu.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = ui32_to_f32((uint32_t)RS1); -set_fp_exceptions; diff --git a/riscv/insns/fcvt_w_d.h b/riscv/insns/fcvt_w_d.h deleted file mode 100644 index 88dc3d3..0000000 --- a/riscv/insns/fcvt_w_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -RD = sext32(f64_to_i32(FRS1, RM, true)); -set_fp_exceptions; diff --git a/riscv/insns/fcvt_w_s.h b/riscv/insns/fcvt_w_s.h deleted file mode 100644 index f14cc19..0000000 --- a/riscv/insns/fcvt_w_s.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -RD = sext32(f32_to_i32(FRS1, RM, true)); -set_fp_exceptions; diff --git a/riscv/insns/fcvt_wu_d.h b/riscv/insns/fcvt_wu_d.h deleted file mode 100644 index 43ad6f6..0000000 --- a/riscv/insns/fcvt_wu_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -RD = sext32(f64_to_ui32(FRS1, RM, true)); -set_fp_exceptions; diff --git a/riscv/insns/fcvt_wu_s.h b/riscv/insns/fcvt_wu_s.h deleted file mode 100644 index ff7a11c..0000000 --- a/riscv/insns/fcvt_wu_s.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -RD = sext32(f32_to_ui32(FRS1, RM, true)); -set_fp_exceptions; diff --git a/riscv/insns/fdiv_d.h b/riscv/insns/fdiv_d.h deleted file mode 100644 index aa00c98..0000000 --- a/riscv/insns/fdiv_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = f64_div(FRS1, FRS2); -set_fp_exceptions; diff --git a/riscv/insns/fdiv_s.h b/riscv/insns/fdiv_s.h deleted file mode 100644 index 8c76587..0000000 --- a/riscv/insns/fdiv_s.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = f32_div(FRS1, FRS2); -set_fp_exceptions; diff --git a/riscv/insns/fence.h b/riscv/insns/fence.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/fence.h +++ /dev/null diff --git a/riscv/insns/fence_g_cv.h b/riscv/insns/fence_g_cv.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/fence_g_cv.h +++ /dev/null diff --git a/riscv/insns/fence_g_v.h b/riscv/insns/fence_g_v.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/fence_g_v.h +++ /dev/null diff --git a/riscv/insns/fence_i.h b/riscv/insns/fence_i.h deleted file mode 100644 index a2dbffe..0000000 --- a/riscv/insns/fence_i.h +++ /dev/null @@ -1 +0,0 @@ -mmu.flush_icache(); diff --git a/riscv/insns/fence_l_cv.h b/riscv/insns/fence_l_cv.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/fence_l_cv.h +++ /dev/null diff --git a/riscv/insns/fence_l_v.h b/riscv/insns/fence_l_v.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/fence_l_v.h +++ /dev/null diff --git a/riscv/insns/feq_d.h b/riscv/insns/feq_d.h deleted file mode 100644 index 9db8760..0000000 --- a/riscv/insns/feq_d.h +++ /dev/null @@ -1,3 +0,0 @@ -require_fp; -RD = f64_eq(FRS1, FRS2); -set_fp_exceptions; diff --git a/riscv/insns/feq_s.h b/riscv/insns/feq_s.h deleted file mode 100644 index 658e8f6..0000000 --- a/riscv/insns/feq_s.h +++ /dev/null @@ -1,3 +0,0 @@ -require_fp; -RD = f32_eq(FRS1, FRS2); -set_fp_exceptions; diff --git a/riscv/insns/fld.h b/riscv/insns/fld.h deleted file mode 100644 index 123dea4..0000000 --- a/riscv/insns/fld.h +++ /dev/null @@ -1,2 +0,0 @@ -require_fp; -FRD = mmu.load_int64(RS1+SIMM); diff --git a/riscv/insns/fle_d.h b/riscv/insns/fle_d.h deleted file mode 100644 index da76187..0000000 --- a/riscv/insns/fle_d.h +++ /dev/null @@ -1,3 +0,0 @@ -require_fp; -RD = f64_le(FRS1, FRS2); -set_fp_exceptions; diff --git a/riscv/insns/fle_s.h b/riscv/insns/fle_s.h deleted file mode 100644 index 9c83a17..0000000 --- a/riscv/insns/fle_s.h +++ /dev/null @@ -1,3 +0,0 @@ -require_fp; -RD = f32_le(FRS1, FRS2); -set_fp_exceptions; diff --git a/riscv/insns/flt_d.h b/riscv/insns/flt_d.h deleted file mode 100644 index 01d135a..0000000 --- a/riscv/insns/flt_d.h +++ /dev/null @@ -1,3 +0,0 @@ -require_fp; -RD = f64_lt(FRS1, FRS2); -set_fp_exceptions; diff --git a/riscv/insns/flt_s.h b/riscv/insns/flt_s.h deleted file mode 100644 index 52eee5d..0000000 --- a/riscv/insns/flt_s.h +++ /dev/null @@ -1,3 +0,0 @@ -require_fp; -RD = f32_lt(FRS1, FRS2); -set_fp_exceptions; diff --git a/riscv/insns/flw.h b/riscv/insns/flw.h deleted file mode 100644 index 335fd7d..0000000 --- a/riscv/insns/flw.h +++ /dev/null @@ -1,2 +0,0 @@ -require_fp; -FRD = mmu.load_int32(RS1+SIMM); diff --git a/riscv/insns/fmadd_d.h b/riscv/insns/fmadd_d.h deleted file mode 100644 index f67853e..0000000 --- a/riscv/insns/fmadd_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = f64_mulAdd(FRS1, FRS2, FRS3); -set_fp_exceptions; diff --git a/riscv/insns/fmadd_s.h b/riscv/insns/fmadd_s.h deleted file mode 100644 index 19db642..0000000 --- a/riscv/insns/fmadd_s.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = f32_mulAdd(FRS1, FRS2, FRS3); -set_fp_exceptions; diff --git a/riscv/insns/fmax_d.h b/riscv/insns/fmax_d.h deleted file mode 100644 index cbbb343..0000000 --- a/riscv/insns/fmax_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -FRD = isNaNF64UI(FRS2) || f64_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */ - ? FRS1 : FRS2; -set_fp_exceptions; diff --git a/riscv/insns/fmax_s.h b/riscv/insns/fmax_s.h deleted file mode 100644 index 8df665f..0000000 --- a/riscv/insns/fmax_s.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -FRD = isNaNF32UI(FRS2) || f32_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */ - ? FRS1 : FRS2; -set_fp_exceptions; diff --git a/riscv/insns/fmin_d.h b/riscv/insns/fmin_d.h deleted file mode 100644 index 3d3d454..0000000 --- a/riscv/insns/fmin_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -FRD = isNaNF64UI(FRS2) || f64_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */ - ? FRS1 : FRS2; -set_fp_exceptions; diff --git a/riscv/insns/fmin_s.h b/riscv/insns/fmin_s.h deleted file mode 100644 index 994c860..0000000 --- a/riscv/insns/fmin_s.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -FRD = isNaNF32UI(FRS2) || f32_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */ - ? FRS1 : FRS2; -set_fp_exceptions; diff --git a/riscv/insns/fmovn.h b/riscv/insns/fmovn.h deleted file mode 100644 index 394b56c..0000000 --- a/riscv/insns/fmovn.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -if (RS1 & 0x1) FRD = FRS2; diff --git a/riscv/insns/fmovz.h b/riscv/insns/fmovz.h deleted file mode 100644 index 7862216..0000000 --- a/riscv/insns/fmovz.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -if (~RS1 & 0x1) FRD = FRS2; diff --git a/riscv/insns/fmsub_d.h b/riscv/insns/fmsub_d.h deleted file mode 100644 index b1e9340..0000000 --- a/riscv/insns/fmsub_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN); -set_fp_exceptions; diff --git a/riscv/insns/fmsub_s.h b/riscv/insns/fmsub_s.h deleted file mode 100644 index d3349f5..0000000 --- a/riscv/insns/fmsub_s.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN); -set_fp_exceptions; diff --git a/riscv/insns/fmul_d.h b/riscv/insns/fmul_d.h deleted file mode 100644 index a8adedd..0000000 --- a/riscv/insns/fmul_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = f64_mul(FRS1, FRS2); -set_fp_exceptions; diff --git a/riscv/insns/fmul_s.h b/riscv/insns/fmul_s.h deleted file mode 100644 index 6475578..0000000 --- a/riscv/insns/fmul_s.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = f32_mul(FRS1, FRS2); -set_fp_exceptions; diff --git a/riscv/insns/fnmadd_d.h b/riscv/insns/fnmadd_d.h deleted file mode 100644 index 1e2ee27..0000000 --- a/riscv/insns/fnmadd_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN; -set_fp_exceptions; diff --git a/riscv/insns/fnmadd_s.h b/riscv/insns/fnmadd_s.h deleted file mode 100644 index 78abb78..0000000 --- a/riscv/insns/fnmadd_s.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = f32_mulAdd(FRS1, FRS2, FRS3) ^ (uint32_t)INT32_MIN; -set_fp_exceptions; diff --git a/riscv/insns/fnmsub_d.h b/riscv/insns/fnmsub_d.h deleted file mode 100644 index ae643a5..0000000 --- a/riscv/insns/fnmsub_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN; -set_fp_exceptions; diff --git a/riscv/insns/fnmsub_s.h b/riscv/insns/fnmsub_s.h deleted file mode 100644 index cbb70ba..0000000 --- a/riscv/insns/fnmsub_s.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN; -set_fp_exceptions; diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h deleted file mode 100644 index 113398e..0000000 --- a/riscv/insns/fsd.h +++ /dev/null @@ -1,2 +0,0 @@ -require_fp; -mmu.store_uint64(RS1+BIMM, FRS2); diff --git a/riscv/insns/fsgnj_d.h b/riscv/insns/fsgnj_d.h deleted file mode 100644 index f66e804..0000000 --- a/riscv/insns/fsgnj_d.h +++ /dev/null @@ -1,2 +0,0 @@ -require_fp; -FRD = (FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN); diff --git a/riscv/insns/fsgnj_s.h b/riscv/insns/fsgnj_s.h deleted file mode 100644 index 35609ac..0000000 --- a/riscv/insns/fsgnj_s.h +++ /dev/null @@ -1,2 +0,0 @@ -require_fp; -FRD = (FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN); diff --git a/riscv/insns/fsgnjn_d.h b/riscv/insns/fsgnjn_d.h deleted file mode 100644 index 22de215..0000000 --- a/riscv/insns/fsgnjn_d.h +++ /dev/null @@ -1,2 +0,0 @@ -require_fp; -FRD = (FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN); diff --git a/riscv/insns/fsgnjn_s.h b/riscv/insns/fsgnjn_s.h deleted file mode 100644 index dd66d71..0000000 --- a/riscv/insns/fsgnjn_s.h +++ /dev/null @@ -1,2 +0,0 @@ -require_fp; -FRD = (FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN); diff --git a/riscv/insns/fsgnjx_d.h b/riscv/insns/fsgnjx_d.h deleted file mode 100644 index 331b6e4..0000000 --- a/riscv/insns/fsgnjx_d.h +++ /dev/null @@ -1,2 +0,0 @@ -require_fp; -FRD = FRS1 ^ (FRS2 & INT64_MIN); diff --git a/riscv/insns/fsgnjx_s.h b/riscv/insns/fsgnjx_s.h deleted file mode 100644 index b455406..0000000 --- a/riscv/insns/fsgnjx_s.h +++ /dev/null @@ -1,2 +0,0 @@ -require_fp; -FRD = FRS1 ^ (FRS2 & (uint32_t)INT32_MIN); diff --git a/riscv/insns/fsqrt_d.h b/riscv/insns/fsqrt_d.h deleted file mode 100644 index 7647c9c..0000000 --- a/riscv/insns/fsqrt_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = f64_sqrt(FRS1); -set_fp_exceptions; diff --git a/riscv/insns/fsqrt_s.h b/riscv/insns/fsqrt_s.h deleted file mode 100644 index 426f241..0000000 --- a/riscv/insns/fsqrt_s.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = f32_sqrt(FRS1); -set_fp_exceptions; diff --git a/riscv/insns/fsub_d.h b/riscv/insns/fsub_d.h deleted file mode 100644 index e25eebb..0000000 --- a/riscv/insns/fsub_d.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = f64_sub(FRS1, FRS2); -set_fp_exceptions; diff --git a/riscv/insns/fsub_s.h b/riscv/insns/fsub_s.h deleted file mode 100644 index 6c64d04..0000000 --- a/riscv/insns/fsub_s.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -softfloat_roundingMode = RM; -FRD = f32_sub(FRS1, FRS2); -set_fp_exceptions; diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h deleted file mode 100644 index 23d3333..0000000 --- a/riscv/insns/fsw.h +++ /dev/null @@ -1,2 +0,0 @@ -require_fp; -mmu.store_uint32(RS1+BIMM, FRS2); diff --git a/riscv/insns/j.h b/riscv/insns/j.h deleted file mode 100644 index 3a4da2a..0000000 --- a/riscv/insns/j.h +++ /dev/null @@ -1 +0,0 @@ -set_pc(JUMP_TARGET); diff --git a/riscv/insns/jal.h b/riscv/insns/jal.h deleted file mode 100644 index 41dc403..0000000 --- a/riscv/insns/jal.h +++ /dev/null @@ -1,2 +0,0 @@ -RA = npc; -set_pc(JUMP_TARGET); diff --git a/riscv/insns/jalr_c.h b/riscv/insns/jalr_c.h deleted file mode 100644 index 91be911..0000000 --- a/riscv/insns/jalr_c.h +++ /dev/null @@ -1,3 +0,0 @@ -reg_t temp = RS1; -RD = npc; -set_pc(temp + SIMM); diff --git a/riscv/insns/jalr_j.h b/riscv/insns/jalr_j.h deleted file mode 100644 index 0d2ef12..0000000 --- a/riscv/insns/jalr_j.h +++ /dev/null @@ -1 +0,0 @@ -#include "insns/jalr_c.h" diff --git a/riscv/insns/jalr_r.h b/riscv/insns/jalr_r.h deleted file mode 100644 index 0d2ef12..0000000 --- a/riscv/insns/jalr_r.h +++ /dev/null @@ -1 +0,0 @@ -#include "insns/jalr_c.h" diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h deleted file mode 100644 index 81ba7de..0000000 --- a/riscv/insns/lb.h +++ /dev/null @@ -1 +0,0 @@ -RD = mmu.load_int8(RS1+SIMM); diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h deleted file mode 100644 index 12c688a..0000000 --- a/riscv/insns/lbu.h +++ /dev/null @@ -1 +0,0 @@ -RD = mmu.load_uint8(RS1+SIMM); diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h deleted file mode 100644 index 940d348..0000000 --- a/riscv/insns/ld.h +++ /dev/null @@ -1,2 +0,0 @@ -require_xpr64; -RD = mmu.load_int64(RS1+SIMM); diff --git a/riscv/insns/lh.h b/riscv/insns/lh.h deleted file mode 100644 index ec25bc4..0000000 --- a/riscv/insns/lh.h +++ /dev/null @@ -1 +0,0 @@ -RD = mmu.load_int16(RS1+SIMM); diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h deleted file mode 100644 index 0999c00..0000000 --- a/riscv/insns/lhu.h +++ /dev/null @@ -1 +0,0 @@ -RD = mmu.load_uint16(RS1+SIMM); diff --git a/riscv/insns/lui.h b/riscv/insns/lui.h deleted file mode 100644 index 6af2a2a..0000000 --- a/riscv/insns/lui.h +++ /dev/null @@ -1 +0,0 @@ -RD = sext32(BIGIMM << IMM_BITS); diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h deleted file mode 100644 index 769c9fd..0000000 --- a/riscv/insns/lw.h +++ /dev/null @@ -1 +0,0 @@ -RD = mmu.load_int32(RS1+SIMM); diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h deleted file mode 100644 index f8f9841..0000000 --- a/riscv/insns/lwu.h +++ /dev/null @@ -1,2 +0,0 @@ -require_xpr64; -RD = mmu.load_uint32(RS1+SIMM); diff --git a/riscv/insns/mffsr.h b/riscv/insns/mffsr.h deleted file mode 100644 index 29debc4..0000000 --- a/riscv/insns/mffsr.h +++ /dev/null @@ -1,2 +0,0 @@ -require_fp; -RD = fsr; diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h deleted file mode 100644 index e0c67ae..0000000 --- a/riscv/insns/mfpcr.h +++ /dev/null @@ -1,68 +0,0 @@ -require_supervisor; - -reg_t val; - -switch(insn.rtype.rs2) -{ - case 0: - val = sr; - break; - case 1: - val = epc; - break; - case 2: - val = badvaddr; - break; - case 3: - val = evec; - break; - case 4: - val = count; - break; - case 5: - val = compare; - break; - case 6: - val = cause; - break; - case 7: - val = 0; - cause &= ~(1 << (IPI_IRQ+CAUSE_IP_SHIFT)); - break; - - case 8: - val = mmu.memsz >> PGSHIFT; - break; - - case 9: - val = mmu.get_ptbr(); - break; - - case 10: - val = id; - break; - - case 11: - val = vecbanks; - break; - - case 12: - val = sim->num_cores(); - break; - - case 17: - fromhost = val = sim->get_fromhost(); - break; - - case 24: - val = pcr_k0; - break; - case 25: - val = pcr_k1; - break; - - default: - val = -1; -} - -RD = sext_xprlen(val); diff --git a/riscv/insns/mftx_d.h b/riscv/insns/mftx_d.h deleted file mode 100644 index 31be4cb..0000000 --- a/riscv/insns/mftx_d.h +++ /dev/null @@ -1,3 +0,0 @@ -require_xpr64; -require_fp; -RD = FRS2; diff --git a/riscv/insns/mftx_s.h b/riscv/insns/mftx_s.h deleted file mode 100644 index 589b33b..0000000 --- a/riscv/insns/mftx_s.h +++ /dev/null @@ -1,2 +0,0 @@ -require_fp; -RD = sext32(FRS2); diff --git a/riscv/insns/movn.h b/riscv/insns/movn.h deleted file mode 100644 index 402d6d3..0000000 --- a/riscv/insns/movn.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -if (RS1 & 0x1) RD = RS2; diff --git a/riscv/insns/movz.h b/riscv/insns/movz.h deleted file mode 100644 index 74cf8a9..0000000 --- a/riscv/insns/movz.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -if (~RS1 & 0x1) RD = RS2; diff --git a/riscv/insns/mtfsr.h b/riscv/insns/mtfsr.h deleted file mode 100644 index cc6f9ea..0000000 --- a/riscv/insns/mtfsr.h +++ /dev/null @@ -1,4 +0,0 @@ -require_fp; -uint32_t tmp = fsr; -set_fsr(RS1); -RD = tmp; diff --git a/riscv/insns/mtpcr.h b/riscv/insns/mtpcr.h deleted file mode 100644 index 46fbfdb..0000000 --- a/riscv/insns/mtpcr.h +++ /dev/null @@ -1,46 +0,0 @@ -require_supervisor; - -switch(insn.rtype.rs2) -{ - case 0: - set_sr(RS1); - break; - case 1: - epc = RS1; - break; - case 3: - evec = RS1; - break; - case 4: - count = RS1; - break; - case 5: - cause &= ~(1 << (TIMER_IRQ+CAUSE_IP_SHIFT)); - compare = RS1; - break; - - case 7: - sim->send_ipi(RS1); - break; - - case 9: - mmu.set_ptbr(RS1); - break; - - case 11: - vecbanks = RS1 & 0xff; - vecbanks_count = __builtin_popcountll(vecbanks); - break; - - case 16: - tohost = RS1; - sim->set_tohost(RS1); - break; - - case 24: - pcr_k0 = RS1; - break; - case 25: - pcr_k1 = RS1; - break; -} diff --git a/riscv/insns/mul.h b/riscv/insns/mul.h deleted file mode 100644 index 770d733..0000000 --- a/riscv/insns/mul.h +++ /dev/null @@ -1 +0,0 @@ -RD = sext_xprlen(RS1 * RS2); diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h deleted file mode 100644 index f771a62..0000000 --- a/riscv/insns/mulh.h +++ /dev/null @@ -1,8 +0,0 @@ -if(xpr64) -{ - int64_t a = RS1; - int64_t b = RS2; - RD = (int128_t(a) * int128_t(b)) >> 64; -} -else - RD = sext32((sext32(RS1) * sext32(RS2)) >> 32); diff --git a/riscv/insns/mulhsu.h b/riscv/insns/mulhsu.h deleted file mode 100644 index c832657..0000000 --- a/riscv/insns/mulhsu.h +++ /dev/null @@ -1,8 +0,0 @@ -if(xpr64) -{ - int64_t a = RS1; - uint64_t b = RS2; - RD = (int128_t(a) * uint128_t(b)) >> 64; -} -else - RD = sext32((sext32(RS1) * reg_t((uint32_t)RS2)) >> 32); diff --git a/riscv/insns/mulhu.h b/riscv/insns/mulhu.h deleted file mode 100644 index 6334426..0000000 --- a/riscv/insns/mulhu.h +++ /dev/null @@ -1,4 +0,0 @@ -if(xpr64) - RD = (uint128_t(RS1) * uint128_t(RS2)) >> 64; -else - RD = sext32(((uint64_t)(uint32_t)RS1 * (uint64_t)(uint32_t)RS2) >> 32); diff --git a/riscv/insns/mulw.h b/riscv/insns/mulw.h deleted file mode 100644 index 7b0a934..0000000 --- a/riscv/insns/mulw.h +++ /dev/null @@ -1,2 +0,0 @@ -require_xpr64; -RD = sext32(RS1 * RS2); diff --git a/riscv/insns/mxtf_d.h b/riscv/insns/mxtf_d.h deleted file mode 100644 index 29792ec..0000000 --- a/riscv/insns/mxtf_d.h +++ /dev/null @@ -1,3 +0,0 @@ -require_xpr64; -require_fp; -FRD = RS1; diff --git a/riscv/insns/mxtf_s.h b/riscv/insns/mxtf_s.h deleted file mode 100644 index 54546ea..0000000 --- a/riscv/insns/mxtf_s.h +++ /dev/null @@ -1,2 +0,0 @@ -require_fp; -FRD = RS1; diff --git a/riscv/insns/or.h b/riscv/insns/or.h deleted file mode 100644 index 07bcac3..0000000 --- a/riscv/insns/or.h +++ /dev/null @@ -1 +0,0 @@ -RD = RS1 | RS2; diff --git a/riscv/insns/ori.h b/riscv/insns/ori.h deleted file mode 100644 index 9561b97..0000000 --- a/riscv/insns/ori.h +++ /dev/null @@ -1 +0,0 @@ -RD = SIMM | RS1; diff --git a/riscv/insns/rdcycle.h b/riscv/insns/rdcycle.h deleted file mode 100644 index 9b966a6..0000000 --- a/riscv/insns/rdcycle.h +++ /dev/null @@ -1 +0,0 @@ -RD = cycle; diff --git a/riscv/insns/rdinstret.h b/riscv/insns/rdinstret.h deleted file mode 100644 index 9b966a6..0000000 --- a/riscv/insns/rdinstret.h +++ /dev/null @@ -1 +0,0 @@ -RD = cycle; diff --git a/riscv/insns/rdnpc.h b/riscv/insns/rdnpc.h deleted file mode 100644 index 5525421..0000000 --- a/riscv/insns/rdnpc.h +++ /dev/null @@ -1 +0,0 @@ -RD = npc; diff --git a/riscv/insns/rdtime.h b/riscv/insns/rdtime.h deleted file mode 100644 index 9b966a6..0000000 --- a/riscv/insns/rdtime.h +++ /dev/null @@ -1 +0,0 @@ -RD = cycle; diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h deleted file mode 100644 index ac82a56..0000000 --- a/riscv/insns/rem.h +++ /dev/null @@ -1,6 +0,0 @@ -if(RS2 == 0) - RD = RS1; -else if(sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1) - RD = 0; -else - RD = sext_xprlen(sext_xprlen(RS1) % sext_xprlen(RS2)); diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h deleted file mode 100644 index c698aca..0000000 --- a/riscv/insns/remu.h +++ /dev/null @@ -1,4 +0,0 @@ -if(RS2 == 0) - RD = RS1; -else - RD = sext_xprlen(zext_xprlen(RS1) % zext_xprlen(RS2)); diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h deleted file mode 100644 index 8234af3..0000000 --- a/riscv/insns/remuw.h +++ /dev/null @@ -1,5 +0,0 @@ -require_xpr64; -if(RS2 == 0) - RD = RS1; -else - RD = sext32(zext_xprlen(RS1) % zext_xprlen(RS2)); diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h deleted file mode 100644 index 93c3858..0000000 --- a/riscv/insns/remw.h +++ /dev/null @@ -1,7 +0,0 @@ -require_xpr64; -if(RS2 == 0) - RD = RS1; -else if(int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1) - RD = 0; -else - RD = sext32(int32_t(RS1) % int32_t(RS2)); diff --git a/riscv/insns/sb.h b/riscv/insns/sb.h deleted file mode 100644 index af5bd10..0000000 --- a/riscv/insns/sb.h +++ /dev/null @@ -1 +0,0 @@ -mmu.store_uint8(RS1+BIMM, RS2); diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h deleted file mode 100644 index 2009149..0000000 --- a/riscv/insns/sd.h +++ /dev/null @@ -1,2 +0,0 @@ -require_xpr64; -mmu.store_uint64(RS1+BIMM, RS2); diff --git a/riscv/insns/sh.h b/riscv/insns/sh.h deleted file mode 100644 index a484e1e..0000000 --- a/riscv/insns/sh.h +++ /dev/null @@ -1 +0,0 @@ -mmu.store_uint16(RS1+BIMM, RS2); diff --git a/riscv/insns/sll.h b/riscv/insns/sll.h deleted file mode 100644 index 86eb966..0000000 --- a/riscv/insns/sll.h +++ /dev/null @@ -1 +0,0 @@ -RD = sext_xprlen(RS1 << (RS2 & (xprlen-1))); diff --git a/riscv/insns/slli.h b/riscv/insns/slli.h deleted file mode 100644 index bfaf430..0000000 --- a/riscv/insns/slli.h +++ /dev/null @@ -1,8 +0,0 @@ -if(xpr64) - RD = RS1 << SHAMT; -else -{ - if(SHAMT & 0x20) - throw trap_illegal_instruction; - RD = sext32(RS1 << SHAMT); -} diff --git a/riscv/insns/slliw.h b/riscv/insns/slliw.h deleted file mode 100644 index 1f6e50d..0000000 --- a/riscv/insns/slliw.h +++ /dev/null @@ -1,2 +0,0 @@ -require_xpr64; -RD = sext32(RS1 << SHAMTW); diff --git a/riscv/insns/sllw.h b/riscv/insns/sllw.h deleted file mode 100644 index f3356d8..0000000 --- a/riscv/insns/sllw.h +++ /dev/null @@ -1,2 +0,0 @@ -require_xpr64; -RD = sext32(RS1 << (RS2 & 0x1F)); diff --git a/riscv/insns/slt.h b/riscv/insns/slt.h deleted file mode 100644 index 5c50534..0000000 --- a/riscv/insns/slt.h +++ /dev/null @@ -1 +0,0 @@ -RD = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2)); diff --git a/riscv/insns/slti.h b/riscv/insns/slti.h deleted file mode 100644 index 1dcd892..0000000 --- a/riscv/insns/slti.h +++ /dev/null @@ -1 +0,0 @@ -RD = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(SIMM)); diff --git a/riscv/insns/sltiu.h b/riscv/insns/sltiu.h deleted file mode 100644 index 45e579b..0000000 --- a/riscv/insns/sltiu.h +++ /dev/null @@ -1 +0,0 @@ -RD = cmp_trunc(RS1) < cmp_trunc(SIMM); diff --git a/riscv/insns/sltu.h b/riscv/insns/sltu.h deleted file mode 100644 index 2c5bdc3..0000000 --- a/riscv/insns/sltu.h +++ /dev/null @@ -1 +0,0 @@ -RD = cmp_trunc(RS1) < cmp_trunc(RS2); diff --git a/riscv/insns/sra.h b/riscv/insns/sra.h deleted file mode 100644 index 7102da0..0000000 --- a/riscv/insns/sra.h +++ /dev/null @@ -1 +0,0 @@ -RD = sext_xprlen(sext_xprlen(RS1) >> (RS2 & (xprlen-1))); diff --git a/riscv/insns/srai.h b/riscv/insns/srai.h deleted file mode 100644 index bb17d27..0000000 --- a/riscv/insns/srai.h +++ /dev/null @@ -1,8 +0,0 @@ -if(xpr64) - RD = sreg_t(RS1) >> SHAMT; -else -{ - if(SHAMT & 0x20) - throw trap_illegal_instruction; - RD = sext32(int32_t(RS1) >> SHAMT); -} diff --git a/riscv/insns/sraiw.h b/riscv/insns/sraiw.h deleted file mode 100644 index 4c56730..0000000 --- a/riscv/insns/sraiw.h +++ /dev/null @@ -1,2 +0,0 @@ -require_xpr64; -RD = sext32(int32_t(RS1) >> SHAMTW); diff --git a/riscv/insns/sraw.h b/riscv/insns/sraw.h deleted file mode 100644 index d178374..0000000 --- a/riscv/insns/sraw.h +++ /dev/null @@ -1,2 +0,0 @@ -require_xpr64; -RD = sext32(int32_t(RS1) >> (RS2 & 0x1F)); diff --git a/riscv/insns/srl.h b/riscv/insns/srl.h deleted file mode 100644 index 8230d27..0000000 --- a/riscv/insns/srl.h +++ /dev/null @@ -1,4 +0,0 @@ -if(xpr64) - RD = RS1 >> (RS2 & 0x3F); -else - RD = sext32((uint32_t)RS1 >> (RS2 & 0x1F)); diff --git a/riscv/insns/srli.h b/riscv/insns/srli.h deleted file mode 100644 index 5378fd1..0000000 --- a/riscv/insns/srli.h +++ /dev/null @@ -1,8 +0,0 @@ -if(xpr64) - RD = RS1 >> SHAMT; -else -{ - if(SHAMT & 0x20) - throw trap_illegal_instruction; - RD = sext32((uint32_t)RS1 >> SHAMT); -} diff --git a/riscv/insns/srliw.h b/riscv/insns/srliw.h deleted file mode 100644 index c400507..0000000 --- a/riscv/insns/srliw.h +++ /dev/null @@ -1,2 +0,0 @@ -require_xpr64; -RD = sext32((uint32_t)RS1 >> SHAMTW); diff --git a/riscv/insns/srlw.h b/riscv/insns/srlw.h deleted file mode 100644 index b206f7c..0000000 --- a/riscv/insns/srlw.h +++ /dev/null @@ -1,2 +0,0 @@ -require_xpr64; -RD = sext32((uint32_t)RS1 >> (RS2 & 0x1F)); diff --git a/riscv/insns/stop.h b/riscv/insns/stop.h deleted file mode 100644 index 791a82c..0000000 --- a/riscv/insns/stop.h +++ /dev/null @@ -1,3 +0,0 @@ -require_vector; -utmode = false; -throw vt_command_stop; diff --git a/riscv/insns/sub.h b/riscv/insns/sub.h deleted file mode 100644 index 2b1e057..0000000 --- a/riscv/insns/sub.h +++ /dev/null @@ -1 +0,0 @@ -RD = sext_xprlen(RS1 - RS2); diff --git a/riscv/insns/subw.h b/riscv/insns/subw.h deleted file mode 100644 index 28db334..0000000 --- a/riscv/insns/subw.h +++ /dev/null @@ -1,3 +0,0 @@ -require_xpr64; -RD = sext32(RS1 - RS2); - diff --git a/riscv/insns/sw.h b/riscv/insns/sw.h deleted file mode 100644 index dbe260f..0000000 --- a/riscv/insns/sw.h +++ /dev/null @@ -1 +0,0 @@ -mmu.store_uint32(RS1+BIMM, RS2); diff --git a/riscv/insns/syscall.h b/riscv/insns/syscall.h deleted file mode 100644 index 2c7199d..0000000 --- a/riscv/insns/syscall.h +++ /dev/null @@ -1 +0,0 @@ -throw trap_syscall; diff --git a/riscv/insns/utidx.h b/riscv/insns/utidx.h deleted file mode 100644 index b3c944c..0000000 --- a/riscv/insns/utidx.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -RD = utidx; diff --git a/riscv/insns/vf.h b/riscv/insns/vf.h deleted file mode 100644 index 7779645..0000000 --- a/riscv/insns/vf.h +++ /dev/null @@ -1,8 +0,0 @@ -require_vector; -for (int i=0; i<VL; i++) -{ - uts[i]->pc = RS1+SIMM; - uts[i]->utmode = true; - while (uts[i]->utmode) - uts[i]->step(1, false); // XXX -} diff --git a/riscv/insns/vfld.h b/riscv/insns/vfld.h deleted file mode 100644 index 9b40470..0000000 --- a/riscv/insns/vfld.h +++ /dev/null @@ -1,3 +0,0 @@ -require_vector; -require_fp; -VEC_LOAD(FRD, load_int64, 8); diff --git a/riscv/insns/vflsegd.h b/riscv/insns/vflsegd.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vflsegd.h +++ /dev/null diff --git a/riscv/insns/vflsegstd.h b/riscv/insns/vflsegstd.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vflsegstd.h +++ /dev/null diff --git a/riscv/insns/vflsegstw.h b/riscv/insns/vflsegstw.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vflsegstw.h +++ /dev/null diff --git a/riscv/insns/vflsegw.h b/riscv/insns/vflsegw.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vflsegw.h +++ /dev/null diff --git a/riscv/insns/vflstd.h b/riscv/insns/vflstd.h deleted file mode 100644 index fa9b32d..0000000 --- a/riscv/insns/vflstd.h +++ /dev/null @@ -1,3 +0,0 @@ -require_vector; -require_fp; -VEC_LOAD(FRD, load_int64, RS2); diff --git a/riscv/insns/vflstw.h b/riscv/insns/vflstw.h deleted file mode 100644 index 716c818..0000000 --- a/riscv/insns/vflstw.h +++ /dev/null @@ -1,3 +0,0 @@ -require_vector; -require_fp; -VEC_LOAD(FRD, load_int32, RS2); diff --git a/riscv/insns/vflw.h b/riscv/insns/vflw.h deleted file mode 100644 index 75fdd04..0000000 --- a/riscv/insns/vflw.h +++ /dev/null @@ -1,3 +0,0 @@ -require_vector; -require_fp; -VEC_LOAD(FRD, load_int32, 4); diff --git a/riscv/insns/vfmst.h b/riscv/insns/vfmst.h deleted file mode 100644 index 20fa123..0000000 --- a/riscv/insns/vfmst.h +++ /dev/null @@ -1,4 +0,0 @@ -require_vector; -require_fp; -demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range!"); -UT_FRD(RS2) = FRS1; diff --git a/riscv/insns/vfmsv.h b/riscv/insns/vfmsv.h deleted file mode 100644 index a9aa876..0000000 --- a/riscv/insns/vfmsv.h +++ /dev/null @@ -1,5 +0,0 @@ -require_vector; -require_fp; -UT_LOOP_START - UT_LOOP_FRD = FRS1; -UT_LOOP_END diff --git a/riscv/insns/vfmts.h b/riscv/insns/vfmts.h deleted file mode 100644 index 6f56b25..0000000 --- a/riscv/insns/vfmts.h +++ /dev/null @@ -1,4 +0,0 @@ -require_vector; -require_fp; -demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range"); -FRD = UT_FRS1(RS2); diff --git a/riscv/insns/vfmvv.h b/riscv/insns/vfmvv.h deleted file mode 100644 index 279da21..0000000 --- a/riscv/insns/vfmvv.h +++ /dev/null @@ -1,5 +0,0 @@ -require_vector; -require_fp; -UT_LOOP_START - UT_LOOP_FRD = UT_LOOP_FRS1; -UT_LOOP_END diff --git a/riscv/insns/vfsd.h b/riscv/insns/vfsd.h deleted file mode 100644 index f619fc8..0000000 --- a/riscv/insns/vfsd.h +++ /dev/null @@ -1,3 +0,0 @@ -require_vector; -require_fp; -VEC_STORE(FRD, store_uint64, 8); diff --git a/riscv/insns/vfssegd.h b/riscv/insns/vfssegd.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vfssegd.h +++ /dev/null diff --git a/riscv/insns/vfssegstd.h b/riscv/insns/vfssegstd.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vfssegstd.h +++ /dev/null diff --git a/riscv/insns/vfssegstw.h b/riscv/insns/vfssegstw.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vfssegstw.h +++ /dev/null diff --git a/riscv/insns/vfssegw.h b/riscv/insns/vfssegw.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vfssegw.h +++ /dev/null diff --git a/riscv/insns/vfsstd.h b/riscv/insns/vfsstd.h deleted file mode 100644 index b3bb260..0000000 --- a/riscv/insns/vfsstd.h +++ /dev/null @@ -1,3 +0,0 @@ -require_vector; -require_fp; -VEC_STORE(FRD, store_uint64, RS2); diff --git a/riscv/insns/vfsstw.h b/riscv/insns/vfsstw.h deleted file mode 100644 index 9cef9b0..0000000 --- a/riscv/insns/vfsstw.h +++ /dev/null @@ -1,3 +0,0 @@ -require_vector; -require_fp; -VEC_STORE(FRD, store_uint32, RS2); diff --git a/riscv/insns/vfsw.h b/riscv/insns/vfsw.h deleted file mode 100644 index 3fe3d3f..0000000 --- a/riscv/insns/vfsw.h +++ /dev/null @@ -1,3 +0,0 @@ -require_vector; -require_fp; -VEC_STORE(FRD, store_uint32, 4); diff --git a/riscv/insns/vlb.h b/riscv/insns/vlb.h deleted file mode 100644 index 618380a..0000000 --- a/riscv/insns/vlb.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -VEC_LOAD(RD, load_int8, 1); diff --git a/riscv/insns/vlbu.h b/riscv/insns/vlbu.h deleted file mode 100644 index f92c8b5..0000000 --- a/riscv/insns/vlbu.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -VEC_LOAD(RD, load_uint8, 1); diff --git a/riscv/insns/vld.h b/riscv/insns/vld.h deleted file mode 100644 index fb7a3c5..0000000 --- a/riscv/insns/vld.h +++ /dev/null @@ -1,3 +0,0 @@ -require_vector; -require_xpr64; -VEC_LOAD(RD, load_int64, 8); diff --git a/riscv/insns/vlh.h b/riscv/insns/vlh.h deleted file mode 100644 index 269c2a8..0000000 --- a/riscv/insns/vlh.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -VEC_LOAD(RD, load_int16, 2); diff --git a/riscv/insns/vlhu.h b/riscv/insns/vlhu.h deleted file mode 100644 index 7a2019d..0000000 --- a/riscv/insns/vlhu.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -VEC_LOAD(RD, load_uint16, 2); diff --git a/riscv/insns/vlsegb.h b/riscv/insns/vlsegb.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vlsegb.h +++ /dev/null diff --git a/riscv/insns/vlsegbu.h b/riscv/insns/vlsegbu.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vlsegbu.h +++ /dev/null diff --git a/riscv/insns/vlsegd.h b/riscv/insns/vlsegd.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vlsegd.h +++ /dev/null diff --git a/riscv/insns/vlsegh.h b/riscv/insns/vlsegh.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vlsegh.h +++ /dev/null diff --git a/riscv/insns/vlseghu.h b/riscv/insns/vlseghu.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vlseghu.h +++ /dev/null diff --git a/riscv/insns/vlsegstb.h b/riscv/insns/vlsegstb.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vlsegstb.h +++ /dev/null diff --git a/riscv/insns/vlsegstbu.h b/riscv/insns/vlsegstbu.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vlsegstbu.h +++ /dev/null diff --git a/riscv/insns/vlsegstd.h b/riscv/insns/vlsegstd.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vlsegstd.h +++ /dev/null diff --git a/riscv/insns/vlsegsth.h b/riscv/insns/vlsegsth.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vlsegsth.h +++ /dev/null diff --git a/riscv/insns/vlsegsthu.h b/riscv/insns/vlsegsthu.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vlsegsthu.h +++ /dev/null diff --git a/riscv/insns/vlsegstw.h b/riscv/insns/vlsegstw.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vlsegstw.h +++ /dev/null diff --git a/riscv/insns/vlsegstwu.h b/riscv/insns/vlsegstwu.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vlsegstwu.h +++ /dev/null diff --git a/riscv/insns/vlsegw.h b/riscv/insns/vlsegw.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vlsegw.h +++ /dev/null diff --git a/riscv/insns/vlsegwu.h b/riscv/insns/vlsegwu.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vlsegwu.h +++ /dev/null diff --git a/riscv/insns/vlstb.h b/riscv/insns/vlstb.h deleted file mode 100644 index 219d90e..0000000 --- a/riscv/insns/vlstb.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -VEC_LOAD(RD, load_int8, RS2); diff --git a/riscv/insns/vlstbu.h b/riscv/insns/vlstbu.h deleted file mode 100644 index 09faa29..0000000 --- a/riscv/insns/vlstbu.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -VEC_LOAD(RD, load_uint8, RS2); diff --git a/riscv/insns/vlstd.h b/riscv/insns/vlstd.h deleted file mode 100644 index 5e5de9c..0000000 --- a/riscv/insns/vlstd.h +++ /dev/null @@ -1,3 +0,0 @@ -require_vector; -require_xpr64; -VEC_LOAD(RD, load_int64, RS2); diff --git a/riscv/insns/vlsth.h b/riscv/insns/vlsth.h deleted file mode 100644 index af6b5b5..0000000 --- a/riscv/insns/vlsth.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -VEC_LOAD(RD, load_int16, RS2); diff --git a/riscv/insns/vlsthu.h b/riscv/insns/vlsthu.h deleted file mode 100644 index 0fe8452..0000000 --- a/riscv/insns/vlsthu.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -VEC_LOAD(RD, load_uint16, RS2); diff --git a/riscv/insns/vlstw.h b/riscv/insns/vlstw.h deleted file mode 100644 index 5375dc0..0000000 --- a/riscv/insns/vlstw.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -VEC_LOAD(RD, load_int32, RS2); diff --git a/riscv/insns/vlstwu.h b/riscv/insns/vlstwu.h deleted file mode 100644 index 328e23f..0000000 --- a/riscv/insns/vlstwu.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -VEC_LOAD(RD, load_uint32, RS2); diff --git a/riscv/insns/vlw.h b/riscv/insns/vlw.h deleted file mode 100644 index 6e35911..0000000 --- a/riscv/insns/vlw.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -VEC_LOAD(RD, load_int32, 4); diff --git a/riscv/insns/vlwu.h b/riscv/insns/vlwu.h deleted file mode 100644 index 4fa1489..0000000 --- a/riscv/insns/vlwu.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -VEC_LOAD(RD, load_uint32, 4); diff --git a/riscv/insns/vmst.h b/riscv/insns/vmst.h deleted file mode 100644 index 7b7cae1..0000000 --- a/riscv/insns/vmst.h +++ /dev/null @@ -1,3 +0,0 @@ -require_vector; -demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range!"); -UT_RD(RS2) = RS1; diff --git a/riscv/insns/vmsv.h b/riscv/insns/vmsv.h deleted file mode 100644 index c6f4c2c..0000000 --- a/riscv/insns/vmsv.h +++ /dev/null @@ -1,4 +0,0 @@ -require_vector; -UT_LOOP_START - UT_LOOP_RD = RS1; -UT_LOOP_END diff --git a/riscv/insns/vmts.h b/riscv/insns/vmts.h deleted file mode 100644 index a69e388..0000000 --- a/riscv/insns/vmts.h +++ /dev/null @@ -1,3 +0,0 @@ -require_vector; -demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range"); -RD = UT_RS1(RS2); diff --git a/riscv/insns/vmvv.h b/riscv/insns/vmvv.h deleted file mode 100644 index 91d63d4..0000000 --- a/riscv/insns/vmvv.h +++ /dev/null @@ -1,4 +0,0 @@ -require_vector; -UT_LOOP_START - UT_LOOP_RD = UT_LOOP_RS1; -UT_LOOP_END diff --git a/riscv/insns/vsb.h b/riscv/insns/vsb.h deleted file mode 100644 index c3d5b9d..0000000 --- a/riscv/insns/vsb.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -VEC_STORE(RD, store_uint8, 1); diff --git a/riscv/insns/vsd.h b/riscv/insns/vsd.h deleted file mode 100644 index 9c02069..0000000 --- a/riscv/insns/vsd.h +++ /dev/null @@ -1,3 +0,0 @@ -require_vector; -require_xpr64; -VEC_STORE(RD, store_uint64, 8); diff --git a/riscv/insns/vsetvl.h b/riscv/insns/vsetvl.h deleted file mode 100644 index c2212ff..0000000 --- a/riscv/insns/vsetvl.h +++ /dev/null @@ -1,3 +0,0 @@ -require_vector; -setvl(RS1); -RD = VL; diff --git a/riscv/insns/vsh.h b/riscv/insns/vsh.h deleted file mode 100644 index 623eda8..0000000 --- a/riscv/insns/vsh.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -VEC_STORE(RD, store_uint16, 2); diff --git a/riscv/insns/vssegb.h b/riscv/insns/vssegb.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vssegb.h +++ /dev/null diff --git a/riscv/insns/vssegd.h b/riscv/insns/vssegd.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vssegd.h +++ /dev/null diff --git a/riscv/insns/vssegh.h b/riscv/insns/vssegh.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vssegh.h +++ /dev/null diff --git a/riscv/insns/vssegstb.h b/riscv/insns/vssegstb.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vssegstb.h +++ /dev/null diff --git a/riscv/insns/vssegstd.h b/riscv/insns/vssegstd.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vssegstd.h +++ /dev/null diff --git a/riscv/insns/vssegsth.h b/riscv/insns/vssegsth.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vssegsth.h +++ /dev/null diff --git a/riscv/insns/vssegstw.h b/riscv/insns/vssegstw.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vssegstw.h +++ /dev/null diff --git a/riscv/insns/vssegw.h b/riscv/insns/vssegw.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vssegw.h +++ /dev/null diff --git a/riscv/insns/vsstb.h b/riscv/insns/vsstb.h deleted file mode 100644 index b83cc50..0000000 --- a/riscv/insns/vsstb.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -VEC_STORE(RD, store_uint8, RS2); diff --git a/riscv/insns/vsstd.h b/riscv/insns/vsstd.h deleted file mode 100644 index 26868d2..0000000 --- a/riscv/insns/vsstd.h +++ /dev/null @@ -1,3 +0,0 @@ -require_vector; -require_xpr64; -VEC_STORE(RD, store_uint64, RS2); diff --git a/riscv/insns/vssth.h b/riscv/insns/vssth.h deleted file mode 100644 index 3904331..0000000 --- a/riscv/insns/vssth.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -VEC_STORE(RD, store_uint16, RS2); diff --git a/riscv/insns/vsstw.h b/riscv/insns/vsstw.h deleted file mode 100644 index 8f05953..0000000 --- a/riscv/insns/vsstw.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -VEC_STORE(RD, store_uint32, RS2); diff --git a/riscv/insns/vsw.h b/riscv/insns/vsw.h deleted file mode 100644 index 662d4e3..0000000 --- a/riscv/insns/vsw.h +++ /dev/null @@ -1,2 +0,0 @@ -require_vector; -VEC_STORE(RD, store_uint32, 4); diff --git a/riscv/insns/vtcfgivl.h b/riscv/insns/vtcfgivl.h deleted file mode 100644 index e69de29..0000000 --- a/riscv/insns/vtcfgivl.h +++ /dev/null diff --git a/riscv/insns/vvcfgivl.h b/riscv/insns/vvcfgivl.h deleted file mode 100644 index 0ded9f8..0000000 --- a/riscv/insns/vvcfgivl.h +++ /dev/null @@ -1,6 +0,0 @@ -require_vector; -nxpr_use = SIMM & 0x3f; -nfpr_use = (SIMM >> 6) & 0x3f; -vcfg(); -setvl(RS1); -RD = VL; diff --git a/riscv/insns/xor.h b/riscv/insns/xor.h deleted file mode 100644 index 49b1783..0000000 --- a/riscv/insns/xor.h +++ /dev/null @@ -1 +0,0 @@ -RD = RS1 ^ RS2; diff --git a/riscv/insns/xori.h b/riscv/insns/xori.h deleted file mode 100644 index 5852aac..0000000 --- a/riscv/insns/xori.h +++ /dev/null @@ -1 +0,0 @@ -RD = SIMM ^ RS1; diff --git a/riscv/mmu.cc b/riscv/mmu.cc deleted file mode 100644 index 7ff937d..0000000 --- a/riscv/mmu.cc +++ /dev/null @@ -1,104 +0,0 @@ -#include "mmu.h" -#include "sim.h" -#include "processor.h" - -mmu_t::mmu_t(char* _mem, size_t _memsz) - : mem(_mem), memsz(_memsz), badvaddr(0), - ptbr(0), supervisor(true), vm_enabled(false), - icsim(NULL), dcsim(NULL), itlbsim(NULL), dtlbsim(NULL) -{ - flush_tlb(); -} - -mmu_t::~mmu_t() -{ -} - -void mmu_t::flush_tlb() -{ - memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag)); - memset(tlb_load_tag, -1, sizeof(tlb_load_tag)); - memset(tlb_store_tag, -1, sizeof(tlb_store_tag)); - flush_icache(); -} - -void mmu_t::flush_icache() -{ - memset(icache_tag, -1, sizeof(icache_tag)); -} - -void* mmu_t::refill(reg_t addr, bool store, bool fetch) -{ - reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES; - reg_t expected_tag = addr & ~(PGSIZE-1); - - reg_t pte = walk(addr); - - reg_t pte_perm = pte & PTE_PERM; - if(supervisor) // shift supervisor permission bits into user perm bits - pte_perm = (pte_perm >> 3) & PTE_PERM; - pte_perm |= pte & PTE_E; - - reg_t perm = (fetch ? PTE_UX : store ? PTE_UW : PTE_UR) | PTE_E; - if(unlikely((pte_perm & perm) != perm)) - { - badvaddr = addr; - throw store ? trap_store_access_fault - : fetch ? trap_instruction_access_fault - : trap_load_access_fault; - } - - tlb_load_tag[idx] = (pte_perm & PTE_UR) ? expected_tag : -1; - tlb_store_tag[idx] = (pte_perm & PTE_UW) ? expected_tag : -1; - tlb_insn_tag[idx] = (pte_perm & PTE_UX) ? expected_tag : -1; - tlb_data[idx] = (long)(pte >> PTE_PPN_SHIFT << PGSHIFT) + (long)mem; - - return (void*)(((long)addr & (PGSIZE-1)) | tlb_data[idx]); -} - -pte_t mmu_t::walk(reg_t addr) -{ - pte_t pte = 0; - - if(!vm_enabled) - { - if(addr < memsz) - pte = PTE_E | PTE_PERM | ((addr >> PGSHIFT) << PTE_PPN_SHIFT); - } - else - { - reg_t base = ptbr; - reg_t ptd; - - int ptshift = (LEVELS-1)*PTIDXBITS; - for(reg_t i = 0; i < LEVELS; i++, ptshift -= PTIDXBITS) - { - reg_t idx = (addr >> (PGSHIFT+ptshift)) & ((1<<PTIDXBITS)-1); - - reg_t pte_addr = base + idx*sizeof(pte_t); - if(pte_addr >= memsz) - break; - - ptd = *(pte_t*)(mem+pte_addr); - if(ptd & PTE_E) - { - // if this PTE is from a larger PT, fake a leaf - // PTE so the TLB will work right - reg_t vpn = addr >> PGSHIFT; - ptd |= (vpn & ((1<<(ptshift))-1)) << PTE_PPN_SHIFT; - - // fault if physical addr is invalid - reg_t ppn = ptd >> PTE_PPN_SHIFT; - if((ppn << PGSHIFT) + (addr & (PGSIZE-1)) < memsz) - pte = ptd; - break; - } - else if(!(ptd & PTE_T)) - break; - - base = (ptd >> PTE_PPN_SHIFT) << PGSHIFT; - } - } - - return pte; -} diff --git a/riscv/mmu.h b/riscv/mmu.h deleted file mode 100644 index e25e90a..0000000 --- a/riscv/mmu.h +++ /dev/null @@ -1,194 +0,0 @@ -#ifndef _RISCV_MMU_H -#define _RISCV_MMU_H - -#include "decode.h" -#include "trap.h" -#include "icsim.h" -#include "common.h" -#include "processor.h" - -class processor_t; - -typedef reg_t pte_t; - -const reg_t LEVELS = 4; -const reg_t PGSHIFT = 12; -const reg_t PGSIZE = 1 << PGSHIFT; -const reg_t PTIDXBITS = PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2); -const reg_t PPN_BITS = 8*sizeof(reg_t) - PGSHIFT; - -#define PTE_T 0x001 // Entry is a page Table descriptor -#define PTE_E 0x002 // Entry is a page table Entry -#define PTE_R 0x004 // Referenced -#define PTE_D 0x008 // Dirty -#define PTE_UX 0x010 // User eXecute permission -#define PTE_UW 0x020 // User Read permission -#define PTE_UR 0x040 // User Write permission -#define PTE_SX 0x080 // Supervisor eXecute permission -#define PTE_SW 0x100 // Supervisor Read permission -#define PTE_SR 0x200 // Supervisor Write permission -#define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX) -#define PTE_PERM_SHIFT 4 -#define PTE_PPN_SHIFT 12 - -class mmu_t -{ -public: - mmu_t(char* _mem, size_t _memsz); - ~mmu_t(); - - #ifdef RISCV_ENABLE_ICSIM - # define dcsim_tick(dcsim, dtlbsim, addr, size, st) \ - do { if(dcsim) (dcsim)->tick(addr, size, st); \ - if(dtlbsim) (dtlbsim)->tick(addr, sizeof(reg_t), false); } while(0) - #else - # define dcsim_tick(dcsim, dtlbsim, addr, size, st) - #endif - - #define load_func(type) \ - type##_t load_##type(reg_t addr) { \ - if(unlikely(addr % sizeof(type##_t))) \ - { \ - badvaddr = addr; \ - throw trap_load_address_misaligned; \ - } \ - void* paddr = translate(addr, false, false); \ - dcsim_tick(dcsim, dtlbsim, paddr-mem, sizeof(type##_t), false); \ - return *(type##_t*)paddr; \ - } - - #define store_func(type) \ - void store_##type(reg_t addr, type##_t val) { \ - if(unlikely(addr % sizeof(type##_t))) \ - { \ - badvaddr = addr; \ - throw trap_store_address_misaligned; \ - } \ - void* paddr = translate(addr, true, false); \ - dcsim_tick(dcsim, dtlbsim, paddr-mem, sizeof(type##_t), true); \ - *(type##_t*)paddr = val; \ - } - - insn_t __attribute__((always_inline)) load_insn(reg_t addr, bool rvc, - insn_func_t* func) - { - insn_t insn; - - #ifdef RISCV_ENABLE_RVC - if(addr % 4 == 2 && rvc) // fetch across word boundary - { - void* addr_lo = translate(addr, false, true); - insn.bits = *(uint16_t*)addr_lo; - - *func = processor_t::dispatch_table - [insn.bits % processor_t::DISPATCH_TABLE_SIZE]; - - if(!INSN_IS_RVC(insn.bits)) - { - void* addr_hi = translate(addr+2, false, true); - insn.bits |= (uint32_t)*(uint16_t*)addr_hi << 16; - } - } - else - #endif - { - reg_t idx = (addr/sizeof(insn_t)) % ICACHE_ENTRIES; - insn_t data = icache_data[idx]; - *func = icache_func[idx]; - if(likely(icache_tag[idx] == addr)) - return data; - - // the processor guarantees alignment based upon rvc mode - void* paddr = translate(addr, false, true); - insn = *(insn_t*)paddr; - - icache_tag[idx] = addr; - icache_data[idx] = insn; - icache_func[idx] = *func = processor_t::dispatch_table - [insn.bits % processor_t::DISPATCH_TABLE_SIZE]; - } - - #ifdef RISCV_ENABLE_ICSIM - if(icsim) - icsim->tick(addr, insn_length(insn.bits), false); - if(itlbsim) - itlbsim->tick(addr, sizeof(reg_t), false); - #endif - - return insn; - } - - load_func(uint8) - load_func(uint16) - load_func(uint32) - load_func(uint64) - - load_func(int8) - load_func(int16) - load_func(int32) - load_func(int64) - - store_func(uint8) - store_func(uint16) - store_func(uint32) - store_func(uint64) - - reg_t get_badvaddr() { return badvaddr; } - reg_t get_ptbr() { return ptbr; } - - void set_supervisor(bool sup) { supervisor = sup; } - void set_vm_enabled(bool en) { vm_enabled = en; } - void set_ptbr(reg_t addr) { ptbr = addr & ~(PGSIZE-1); flush_tlb(); } - - void set_icsim(icsim_t* _icsim) { icsim = _icsim; } - void set_dcsim(icsim_t* _dcsim) { dcsim = _dcsim; } - void set_itlbsim(icsim_t* _itlbsim) { itlbsim = _itlbsim; } - void set_dtlbsim(icsim_t* _dtlbsim) { dtlbsim = _dtlbsim; } - - void flush_tlb(); - void flush_icache(); - -private: - char* mem; - size_t memsz; - reg_t badvaddr; - - reg_t ptbr; - bool supervisor; - bool vm_enabled; - - static const reg_t TLB_ENTRIES = 256; - long tlb_data[TLB_ENTRIES]; - reg_t tlb_insn_tag[TLB_ENTRIES]; - reg_t tlb_load_tag[TLB_ENTRIES]; - reg_t tlb_store_tag[TLB_ENTRIES]; - - static const reg_t ICACHE_ENTRIES = 256; - insn_t icache_data[ICACHE_ENTRIES]; - insn_func_t icache_func[ICACHE_ENTRIES]; - reg_t icache_tag[ICACHE_ENTRIES]; - - icsim_t* icsim; - icsim_t* dcsim; - icsim_t* itlbsim; - icsim_t* dtlbsim; - - void* refill(reg_t addr, bool store, bool fetch); - pte_t walk(reg_t addr); - - void* translate(reg_t addr, bool store, bool fetch) - { - reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES; - - reg_t* tlb_tag = fetch ? tlb_insn_tag : store ? tlb_store_tag :tlb_load_tag; - reg_t expected_tag = addr & ~(PGSIZE-1); - if(likely(tlb_tag[idx] == expected_tag)) - return (void*)(((long)addr & (PGSIZE-1)) | tlb_data[idx]); - - return refill(addr, store, fetch); - } - - friend class processor_t; -}; - -#endif diff --git a/riscv/opcodes.h b/riscv/opcodes.h deleted file mode 100644 index b37b833..0000000 --- a/riscv/opcodes.h +++ /dev/null @@ -1,272 +0,0 @@ -DECLARE_INSN(movn, 0x6f7, 0x1ffff) -DECLARE_INSN(vfsstw, 0x150f, 0x1ffff) -DECLARE_INSN(remuw, 0x7bb, 0x1ffff) -DECLARE_INSN(fmin_d, 0x180d3, 0x1ffff) -DECLARE_INSN(vlsthu, 0x128b, 0x1ffff) -DECLARE_INSN(c_swsp, 0x8, 0x1f) -DECLARE_INSN(bltu, 0x363, 0x3ff) -DECLARE_INSN(vlsegstwu, 0xb0b, 0xfff) -DECLARE_INSN(movz, 0x2f7, 0x1ffff) -DECLARE_INSN(fcvt_lu_s, 0x9053, 0x3ff1ff) -DECLARE_INSN(fence_l_cv, 0x32f, 0x3ff) -DECLARE_INSN(fmin_s, 0x18053, 0x1ffff) -DECLARE_INSN(c_lw0, 0x12, 0x801f) -DECLARE_INSN(slliw, 0x9b, 0x3f83ff) -DECLARE_INSN(lb, 0x3, 0x3ff) -DECLARE_INSN(vlwu, 0x30b, 0x3fffff) -DECLARE_INSN(fcvt_d_l, 0xc0d3, 0x3ff1ff) -DECLARE_INSN(lh, 0x83, 0x3ff) -DECLARE_INSN(fcvt_d_w, 0xe0d3, 0x3ff1ff) -DECLARE_INSN(lw, 0x103, 0x3ff) -DECLARE_INSN(add, 0x33, 0x1ffff) -DECLARE_INSN(fcvt_d_s, 0x100d3, 0x3ff1ff) -DECLARE_INSN(fence_g_v, 0x2af, 0x3ff) -DECLARE_INSN(mfpcr, 0x17b, 0x7c1ffff) -DECLARE_INSN(c_fsd, 0x18, 0x1f) -DECLARE_INSN(fmax_d, 0x190d3, 0x1ffff) -DECLARE_INSN(bne, 0xe3, 0x3ff) -DECLARE_INSN(rdcycle, 0x277, 0x7ffffff) -DECLARE_INSN(fcvt_s_d, 0x11053, 0x3ff1ff) -DECLARE_INSN(vlh, 0x8b, 0x3fffff) -DECLARE_INSN(bgeu, 0x3e3, 0x3ff) -DECLARE_INSN(vflstd, 0x158b, 0x1ffff) -DECLARE_INSN(c_li, 0x0, 0x1f) -DECLARE_INSN(di, 0xfb, 0x7ffffff) -DECLARE_INSN(sltiu, 0x193, 0x3ff) -DECLARE_INSN(mtpcr, 0x1fb, 0xf801ffff) -DECLARE_INSN(vlb, 0xb, 0x3fffff) -DECLARE_INSN(stop, 0x177, 0xffffffff) -DECLARE_INSN(vld, 0x18b, 0x3fffff) -DECLARE_INSN(c_slli, 0x19, 0x1c1f) -DECLARE_INSN(break, 0xf7, 0xffffffff) -DECLARE_INSN(cflush, 0x2fb, 0xffffffff) -DECLARE_INSN(fcvt_s_w, 0xe053, 0x3ff1ff) -DECLARE_INSN(vflstw, 0x150b, 0x1ffff) -DECLARE_INSN(mul, 0x433, 0x1ffff) -DECLARE_INSN(c_lw, 0xa, 0x1f) -DECLARE_INSN(vlw, 0x10b, 0x3fffff) -DECLARE_INSN(vssegstw, 0x90f, 0xfff) -DECLARE_INSN(amominu_d, 0x19ab, 0x1ffff) -DECLARE_INSN(c_sdsp, 0x6, 0x1f) -DECLARE_INSN(utidx, 0x1f7, 0x7ffffff) -DECLARE_INSN(srli, 0x293, 0x3f03ff) -DECLARE_INSN(c_srli, 0x819, 0x1c1f) -DECLARE_INSN(c_ldsp, 0x4, 0x1f) -DECLARE_INSN(c_flw, 0x14, 0x1f) -DECLARE_INSN(c_srai32, 0x1419, 0x1c1f) -DECLARE_INSN(amominu_w, 0x192b, 0x1ffff) -DECLARE_INSN(divuw, 0x6bb, 0x1ffff) -DECLARE_INSN(mulw, 0x43b, 0x1ffff) -DECLARE_INSN(vssegstd, 0x98f, 0xfff) -DECLARE_INSN(srlw, 0x2bb, 0x1ffff) -DECLARE_INSN(vssegstb, 0x80f, 0xfff) -DECLARE_INSN(mftx_d, 0x1c0d3, 0x7c1ffff) -DECLARE_INSN(div, 0x633, 0x1ffff) -DECLARE_INSN(c_ld, 0x9, 0x1f) -DECLARE_INSN(mftx_s, 0x1c053, 0x7c1ffff) -DECLARE_INSN(vssegsth, 0x88f, 0xfff) -DECLARE_INSN(vvcfgivl, 0xf3, 0x3ff) -DECLARE_INSN(j, 0x67, 0x7f) -DECLARE_INSN(ei, 0x7b, 0x7ffffff) -DECLARE_INSN(fence, 0x12f, 0x3ff) -DECLARE_INSN(vsw, 0x10f, 0x3fffff) -DECLARE_INSN(fnmsub_s, 0x4b, 0x1ff) -DECLARE_INSN(vfssegstd, 0xd8f, 0xfff) -DECLARE_INSN(fcvt_l_s, 0x8053, 0x3ff1ff) -DECLARE_INSN(fle_s, 0x17053, 0x1ffff) -DECLARE_INSN(vsb, 0xf, 0x3fffff) -DECLARE_INSN(mffsr, 0x1d053, 0x7ffffff) -DECLARE_INSN(fdiv_s, 0x3053, 0x1f1ff) -DECLARE_INSN(vlstbu, 0x120b, 0x1ffff) -DECLARE_INSN(vsetvl, 0x2f3, 0x3fffff) -DECLARE_INSN(fle_d, 0x170d3, 0x1ffff) -DECLARE_INSN(fence_i, 0xaf, 0x3ff) -DECLARE_INSN(vlsegbu, 0x220b, 0x1ffff) -DECLARE_INSN(fnmsub_d, 0xcb, 0x1ff) -DECLARE_INSN(addw, 0x3b, 0x1ffff) -DECLARE_INSN(sll, 0xb3, 0x1ffff) -DECLARE_INSN(xor, 0x233, 0x1ffff) -DECLARE_INSN(sub, 0x10033, 0x1ffff) -DECLARE_INSN(eret, 0x27b, 0xffffffff) -DECLARE_INSN(blt, 0x263, 0x3ff) -DECLARE_INSN(vsstw, 0x110f, 0x1ffff) -DECLARE_INSN(mtfsr, 0x1f053, 0x3fffff) -DECLARE_INSN(vssth, 0x108f, 0x1ffff) -DECLARE_INSN(rem, 0x733, 0x1ffff) -DECLARE_INSN(srliw, 0x29b, 0x3f83ff) -DECLARE_INSN(lui, 0x37, 0x7f) -DECLARE_INSN(vsstb, 0x100f, 0x1ffff) -DECLARE_INSN(fcvt_s_lu, 0xd053, 0x3ff1ff) -DECLARE_INSN(vsstd, 0x118f, 0x1ffff) -DECLARE_INSN(addi, 0x13, 0x3ff) -DECLARE_INSN(vfmst, 0x1173, 0x1ffff) -DECLARE_INSN(mulh, 0x4b3, 0x1ffff) -DECLARE_INSN(fmul_s, 0x2053, 0x1f1ff) -DECLARE_INSN(vlsegsthu, 0xa8b, 0xfff) -DECLARE_INSN(srai, 0x10293, 0x3f03ff) -DECLARE_INSN(amoand_d, 0x9ab, 0x1ffff) -DECLARE_INSN(flt_d, 0x160d3, 0x1ffff) -DECLARE_INSN(sraw, 0x102bb, 0x1ffff) -DECLARE_INSN(fmul_d, 0x20d3, 0x1f1ff) -DECLARE_INSN(ld, 0x183, 0x3ff) -DECLARE_INSN(ori, 0x313, 0x3ff) -DECLARE_INSN(flt_s, 0x16053, 0x1ffff) -DECLARE_INSN(addiw, 0x1b, 0x3ff) -DECLARE_INSN(amoand_w, 0x92b, 0x1ffff) -DECLARE_INSN(feq_s, 0x15053, 0x1ffff) -DECLARE_INSN(fsgnjx_d, 0x70d3, 0x1ffff) -DECLARE_INSN(sra, 0x102b3, 0x1ffff) -DECLARE_INSN(c_lwsp, 0x5, 0x1f) -DECLARE_INSN(bge, 0x2e3, 0x3ff) -DECLARE_INSN(c_add3, 0x1c, 0x31f) -DECLARE_INSN(sraiw, 0x1029b, 0x3f83ff) -DECLARE_INSN(vssegd, 0x218f, 0x1ffff) -DECLARE_INSN(srl, 0x2b3, 0x1ffff) -DECLARE_INSN(vfmts, 0x1973, 0x1ffff) -DECLARE_INSN(fsgnjx_s, 0x7053, 0x1ffff) -DECLARE_INSN(vfmsv, 0x973, 0x3fffff) -DECLARE_INSN(feq_d, 0x150d3, 0x1ffff) -DECLARE_INSN(fcvt_d_wu, 0xf0d3, 0x3ff1ff) -DECLARE_INSN(vmts, 0x1873, 0x1ffff) -DECLARE_INSN(or, 0x333, 0x1ffff) -DECLARE_INSN(rdinstret, 0xa77, 0x7ffffff) -DECLARE_INSN(fcvt_wu_d, 0xb0d3, 0x3ff1ff) -DECLARE_INSN(subw, 0x1003b, 0x1ffff) -DECLARE_INSN(jalr_c, 0x6b, 0x3ff) -DECLARE_INSN(fmax_s, 0x19053, 0x1ffff) -DECLARE_INSN(amomaxu_d, 0x1dab, 0x1ffff) -DECLARE_INSN(c_slliw, 0x1819, 0x1c1f) -DECLARE_INSN(jalr_j, 0x16b, 0x3ff) -DECLARE_INSN(c_fld, 0x15, 0x1f) -DECLARE_INSN(vlstw, 0x110b, 0x1ffff) -DECLARE_INSN(vlsth, 0x108b, 0x1ffff) -DECLARE_INSN(xori, 0x213, 0x3ff) -DECLARE_INSN(jalr_r, 0xeb, 0x3ff) -DECLARE_INSN(amomaxu_w, 0x1d2b, 0x1ffff) -DECLARE_INSN(fcvt_wu_s, 0xb053, 0x3ff1ff) -DECLARE_INSN(vlstb, 0x100b, 0x1ffff) -DECLARE_INSN(vlstd, 0x118b, 0x1ffff) -DECLARE_INSN(c_ld0, 0x8012, 0x801f) -DECLARE_INSN(rdtime, 0x677, 0x7ffffff) -DECLARE_INSN(andi, 0x393, 0x3ff) -DECLARE_INSN(c_srli32, 0xc19, 0x1c1f) -DECLARE_INSN(fsgnjn_d, 0x60d3, 0x1ffff) -DECLARE_INSN(fnmadd_s, 0x4f, 0x1ff) -DECLARE_INSN(jal, 0x6f, 0x7f) -DECLARE_INSN(lwu, 0x303, 0x3ff) -DECLARE_INSN(vlsegstbu, 0xa0b, 0xfff) -DECLARE_INSN(c_beq, 0x10, 0x1f) -DECLARE_INSN(vlhu, 0x28b, 0x3fffff) -DECLARE_INSN(vfsstd, 0x158f, 0x1ffff) -DECLARE_INSN(c_bne, 0x11, 0x1f) -DECLARE_INSN(fnmadd_d, 0xcf, 0x1ff) -DECLARE_INSN(fence_g_cv, 0x3af, 0x3ff) -DECLARE_INSN(amoadd_d, 0x1ab, 0x1ffff) -DECLARE_INSN(c_sw, 0xd, 0x1f) -DECLARE_INSN(amomax_w, 0x152b, 0x1ffff) -DECLARE_INSN(c_move, 0x2, 0x801f) -DECLARE_INSN(fmovn, 0xef7, 0x1ffff) -DECLARE_INSN(c_fsw, 0x16, 0x1f) -DECLARE_INSN(c_j, 0x8002, 0x801f) -DECLARE_INSN(mulhsu, 0x533, 0x1ffff) -DECLARE_INSN(c_sd, 0xc, 0x1f) -DECLARE_INSN(amoadd_w, 0x12b, 0x1ffff) -DECLARE_INSN(fcvt_d_lu, 0xd0d3, 0x3ff1ff) -DECLARE_INSN(amomax_d, 0x15ab, 0x1ffff) -DECLARE_INSN(fcvt_w_d, 0xa0d3, 0x3ff1ff) -DECLARE_INSN(fmovz, 0xaf7, 0x1ffff) -DECLARE_INSN(c_or3, 0x21c, 0x31f) -DECLARE_INSN(vmvv, 0x73, 0x3fffff) -DECLARE_INSN(vfssegstw, 0xd0f, 0xfff) -DECLARE_INSN(slt, 0x133, 0x1ffff) -DECLARE_INSN(mxtf_d, 0x1e0d3, 0x3fffff) -DECLARE_INSN(sllw, 0xbb, 0x1ffff) -DECLARE_INSN(amoor_d, 0xdab, 0x1ffff) -DECLARE_INSN(slti, 0x113, 0x3ff) -DECLARE_INSN(remu, 0x7b3, 0x1ffff) -DECLARE_INSN(flw, 0x107, 0x3ff) -DECLARE_INSN(remw, 0x73b, 0x1ffff) -DECLARE_INSN(sltu, 0x1b3, 0x1ffff) -DECLARE_INSN(slli, 0x93, 0x3f03ff) -DECLARE_INSN(c_and3, 0x31c, 0x31f) -DECLARE_INSN(vssegw, 0x210f, 0x1ffff) -DECLARE_INSN(amoor_w, 0xd2b, 0x1ffff) -DECLARE_INSN(vsd, 0x18f, 0x3fffff) -DECLARE_INSN(beq, 0x63, 0x3ff) -DECLARE_INSN(fld, 0x187, 0x3ff) -DECLARE_INSN(mxtf_s, 0x1e053, 0x3fffff) -DECLARE_INSN(fsub_s, 0x1053, 0x1f1ff) -DECLARE_INSN(and, 0x3b3, 0x1ffff) -DECLARE_INSN(vtcfgivl, 0x1f3, 0x3ff) -DECLARE_INSN(lbu, 0x203, 0x3ff) -DECLARE_INSN(vf, 0x3f3, 0xf80003ff) -DECLARE_INSN(vlsegstw, 0x90b, 0xfff) -DECLARE_INSN(syscall, 0x77, 0xffffffff) -DECLARE_INSN(fsgnj_s, 0x5053, 0x1ffff) -DECLARE_INSN(c_addi, 0x1, 0x1f) -DECLARE_INSN(vfmvv, 0x173, 0x3fffff) -DECLARE_INSN(vlstwu, 0x130b, 0x1ffff) -DECLARE_INSN(c_sub3, 0x11c, 0x31f) -DECLARE_INSN(vsh, 0x8f, 0x3fffff) -DECLARE_INSN(vlsegstb, 0x80b, 0xfff) -DECLARE_INSN(vlsegstd, 0x98b, 0xfff) -DECLARE_INSN(vflsegd, 0x258b, 0x1ffff) -DECLARE_INSN(vflsegw, 0x250b, 0x1ffff) -DECLARE_INSN(vlsegsth, 0x88b, 0xfff) -DECLARE_INSN(fsgnj_d, 0x50d3, 0x1ffff) -DECLARE_INSN(vflsegstw, 0xd0b, 0xfff) -DECLARE_INSN(c_sub, 0x801a, 0x801f) -DECLARE_INSN(mulhu, 0x5b3, 0x1ffff) -DECLARE_INSN(fcvt_l_d, 0x80d3, 0x3ff1ff) -DECLARE_INSN(vmsv, 0x873, 0x3fffff) -DECLARE_INSN(vmst, 0x1073, 0x1ffff) -DECLARE_INSN(fadd_d, 0xd3, 0x1f1ff) -DECLARE_INSN(fcvt_s_wu, 0xf053, 0x3ff1ff) -DECLARE_INSN(rdnpc, 0x26b, 0x7ffffff) -DECLARE_INSN(fcvt_s_l, 0xc053, 0x3ff1ff) -DECLARE_INSN(vflsegstd, 0xd8b, 0xfff) -DECLARE_INSN(c_add, 0x1a, 0x801f) -DECLARE_INSN(fcvt_lu_d, 0x90d3, 0x3ff1ff) -DECLARE_INSN(vfld, 0x58b, 0x3fffff) -DECLARE_INSN(fsub_d, 0x10d3, 0x1f1ff) -DECLARE_INSN(fmadd_s, 0x43, 0x1ff) -DECLARE_INSN(fcvt_w_s, 0xa053, 0x3ff1ff) -DECLARE_INSN(vssegh, 0x208f, 0x1ffff) -DECLARE_INSN(fsqrt_s, 0x4053, 0x3ff1ff) -DECLARE_INSN(c_srai, 0x1019, 0x1c1f) -DECLARE_INSN(amomin_w, 0x112b, 0x1ffff) -DECLARE_INSN(fsgnjn_s, 0x6053, 0x1ffff) -DECLARE_INSN(c_slli32, 0x419, 0x1c1f) -DECLARE_INSN(vlsegwu, 0x230b, 0x1ffff) -DECLARE_INSN(vfsw, 0x50f, 0x3fffff) -DECLARE_INSN(amoswap_d, 0x5ab, 0x1ffff) -DECLARE_INSN(fence_l_v, 0x22f, 0x3ff) -DECLARE_INSN(fsqrt_d, 0x40d3, 0x3ff1ff) -DECLARE_INSN(vflw, 0x50b, 0x3fffff) -DECLARE_INSN(fdiv_d, 0x30d3, 0x1f1ff) -DECLARE_INSN(fmadd_d, 0xc3, 0x1ff) -DECLARE_INSN(divw, 0x63b, 0x1ffff) -DECLARE_INSN(amomin_d, 0x11ab, 0x1ffff) -DECLARE_INSN(divu, 0x6b3, 0x1ffff) -DECLARE_INSN(amoswap_w, 0x52b, 0x1ffff) -DECLARE_INSN(vfsd, 0x58f, 0x3fffff) -DECLARE_INSN(fadd_s, 0x53, 0x1f1ff) -DECLARE_INSN(vlsegb, 0x200b, 0x1ffff) -DECLARE_INSN(fsd, 0x1a7, 0x3ff) -DECLARE_INSN(vlsegd, 0x218b, 0x1ffff) -DECLARE_INSN(vlsegh, 0x208b, 0x1ffff) -DECLARE_INSN(sw, 0x123, 0x3ff) -DECLARE_INSN(fmsub_s, 0x47, 0x1ff) -DECLARE_INSN(vfssegw, 0x250f, 0x1ffff) -DECLARE_INSN(c_addiw, 0x1d, 0x1f) -DECLARE_INSN(lhu, 0x283, 0x3ff) -DECLARE_INSN(sh, 0xa3, 0x3ff) -DECLARE_INSN(vlsegw, 0x210b, 0x1ffff) -DECLARE_INSN(fsw, 0x127, 0x3ff) -DECLARE_INSN(vlbu, 0x20b, 0x3fffff) -DECLARE_INSN(sb, 0x23, 0x3ff) -DECLARE_INSN(fmsub_d, 0xc7, 0x1ff) -DECLARE_INSN(vlseghu, 0x228b, 0x1ffff) -DECLARE_INSN(vssegb, 0x200f, 0x1ffff) -DECLARE_INSN(vfssegd, 0x258f, 0x1ffff) -DECLARE_INSN(sd, 0x1a3, 0x3ff) diff --git a/riscv/processor.cc b/riscv/processor.cc deleted file mode 100644 index e86536e..0000000 --- a/riscv/processor.cc +++ /dev/null @@ -1,273 +0,0 @@ -#include "processor.h" -#include <bfd.h> -#include <dis-asm.h> -#include <cmath> -#include <cstdlib> -#include <iostream> -#include "common.h" -#include "config.h" -#include "sim.h" -#include "icsim.h" - -processor_t::processor_t(sim_t* _sim, mmu_t* _mmu) - : sim(_sim), mmu(*_mmu) -{ - // a few assumptions about endianness, including freg_t union - static_assert(BYTE_ORDER == LITTLE_ENDIAN); - static_assert(sizeof(freg_t) == 8); - static_assert(sizeof(reg_t) == 8); - - static_assert(sizeof(insn_t) == 4); - static_assert(sizeof(uint128_t) == 16 && sizeof(int128_t) == 16); - - icsim = NULL; - dcsim = NULL; - itlbsim = NULL; - dtlbsim = NULL; - - reset(); -} - -processor_t::~processor_t() -{ - if(icsim) - icsim->print_stats(); - delete icsim; - - if(itlbsim) - itlbsim->print_stats(); - delete itlbsim; - - if(dcsim) - dcsim->print_stats(); - delete dcsim; - - if(dtlbsim) - dtlbsim->print_stats(); - delete dtlbsim; -} - -void processor_t::init(uint32_t _id, icsim_t* default_icache, - icsim_t* default_dcache) -{ - id = _id; - - for (int i=0; i<MAX_UTS; i++) - { - uts[i] = new processor_t(sim, &mmu); - uts[i]->id = id; - uts[i]->set_sr(uts[i]->sr | SR_EF); - uts[i]->set_sr(uts[i]->sr | SR_EV); - uts[i]->utidx = i; - } - - #ifdef RISCV_ENABLE_ICSIM - icsim = new icsim_t(*default_icache); - mmu.set_icsim(icsim); - itlbsim = new icsim_t(1, 8, 4096, "ITLB"); - mmu.set_itlbsim(itlbsim); - #endif - #ifdef RISCV_ENABLE_ICSIM - dcsim = new icsim_t(*default_dcache); - mmu.set_dcsim(dcsim); - dtlbsim = new icsim_t(1, 8, 4096, "DTLB"); - mmu.set_dtlbsim(dtlbsim); - #endif -} - -void processor_t::reset() -{ - run = false; - - memset(XPR,0,sizeof(XPR)); - memset(FPR,0,sizeof(FPR)); - - pc = 0; - evec = 0; - epc = 0; - badvaddr = 0; - cause = 0; - pcr_k0 = 0; - pcr_k1 = 0; - tohost = 0; - fromhost = 0; - count = 0; - compare = 0; - cycle = 0; - set_sr(SR_S | SR_SX); // SX ignored if 64b mode not supported - set_fsr(0); - - // vector stuff - vecbanks = 0xff; - vecbanks_count = 8; - utidx = -1; - vlmax = 32; - vl = 0; - nxfpr_bank = 256; - nxpr_use = 32; - nfpr_use = 32; - for (int i=0; i<MAX_UTS; i++) - uts[i] = NULL; -} - -void processor_t::set_sr(uint32_t val) -{ - sr = val & ~SR_ZERO; -#ifndef RISCV_ENABLE_64BIT - sr &= ~(SR_SX | SR_UX); -#endif -#ifndef RISCV_ENABLE_FPU - sr &= ~SR_EF; -#endif -#ifndef RISCV_ENABLE_RVC - sr &= ~SR_EC; -#endif -#ifndef RISCV_ENABLE_VEC - sr &= ~SR_EV; -#endif - - mmu.set_vm_enabled(sr & SR_VM); - mmu.set_supervisor(sr & SR_S); - mmu.flush_tlb(); - - xprlen = ((sr & SR_S) ? (sr & SR_SX) : (sr & SR_UX)) ? 64 : 32; -} - -void processor_t::set_fsr(uint32_t val) -{ - fsr = val & ~FSR_ZERO; -} - -void processor_t::vcfg() -{ - if (nxpr_use + nfpr_use < 2) - vlmax = nxfpr_bank * vecbanks_count; - else - vlmax = (nxfpr_bank / (nxpr_use + nfpr_use - 1)) * vecbanks_count; - - vlmax = std::min(vlmax, MAX_UTS); -} - -void processor_t::setvl(int vlapp) -{ - vl = std::min(vlmax, vlapp); -} - -void processor_t::take_interrupt() -{ - uint32_t interrupts = (cause & CAUSE_IP) >> CAUSE_IP_SHIFT; - interrupts &= (sr & SR_IM) >> SR_IM_SHIFT; - - if(interrupts && (sr & SR_ET)) - throw trap_interrupt; -} - -void processor_t::step(size_t n, bool noisy) -{ - if(!run) - return; - - size_t i = 0; - while(1) try - { - take_interrupt(); - - mmu_t& _mmu = mmu; - insn_t insn; - insn_func_t func; - reg_t npc = pc; - #define execute_insn(noisy) \ - do { \ - insn = _mmu.load_insn(npc, sr & SR_EC, &func); \ - if(noisy) disasm(insn,pc); \ - npc = func(this, insn, npc); \ - pc = npc; \ - } while(0) - - if(noisy) for( ; i < n; i++) - execute_insn(true); - else - { - for( ; n > 3 && i < n-3; i+=4) - { - execute_insn(false); - execute_insn(false); - execute_insn(false); - execute_insn(false); - } - for( ; i < n; i++) - execute_insn(false); - } - - break; - } - catch(trap_t t) - { - i++; - take_trap(t,noisy); - } - catch(vt_command_t cmd) - { - i++; - if (cmd == vt_command_stop) - break; - } - catch(halt_t t) - { - reset(); - return; - } - - cycle += i; - - typeof(count) old_count = count; - typeof(count) max_count = -1; - count += i; - if(old_count < compare && (count >= compare || old_count > max_count-i)) - cause |= 1 << (TIMER_IRQ+CAUSE_IP_SHIFT); -} - -void processor_t::take_trap(trap_t t, bool noisy) -{ - demand(t < NUM_TRAPS, "internal error: bad trap number %d", int(t)); - demand(sr & SR_ET, "error mode on core %d!\ntrap %s, pc 0x%016llx", - id, trap_name(t), (unsigned long long)pc); - if(noisy) - printf("core %3d: trap %s, pc 0x%016llx\n", - id, trap_name(t), (unsigned long long)pc); - - set_sr((((sr & ~SR_ET) | SR_S) & ~SR_PS) | ((sr & SR_S) ? SR_PS : 0)); - cause = (cause & ~CAUSE_EXCCODE) | (t << CAUSE_EXCCODE_SHIFT); - epc = pc; - pc = evec; - badvaddr = mmu.get_badvaddr(); -} - -void processor_t::deliver_ipi() -{ - cause |= 1 << (IPI_IRQ+CAUSE_IP_SHIFT); - run = true; -} - -void processor_t::disasm(insn_t insn, reg_t pc) -{ - printf("core %3d: 0x%016llx (0x%08x) ",id,(unsigned long long)pc,insn.bits); - - #ifdef RISCV_HAVE_LIBOPCODES - disassemble_info info; - INIT_DISASSEMBLE_INFO(info, stdout, fprintf); - info.flavour = bfd_target_unknown_flavour; - info.arch = bfd_arch_mips; - info.mach = 101; // XXX bfd_mach_mips_riscv requires modified bfd.h - info.endian = BFD_ENDIAN_LITTLE; - info.buffer = (bfd_byte*)&insn; - info.buffer_length = sizeof(insn); - info.buffer_vma = pc; - - int ret = print_insn_little_mips(pc, &info); - demand(ret == insn_length(insn.bits), "disasm bug!"); - #else - printf("unknown"); - #endif - printf("\n"); -} diff --git a/riscv/processor.h b/riscv/processor.h deleted file mode 100644 index 8b2d2bc..0000000 --- a/riscv/processor.h +++ /dev/null @@ -1,97 +0,0 @@ -#ifndef _RISCV_PROCESSOR_H -#define _RISCV_PROCESSOR_H - -#include "decode.h" -#include <cstring> -#include "trap.h" -#include "icsim.h" - -#define MAX_UTS 2048 - -class processor_t; -class mmu_t; -typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t); -class sim_t; - -class processor_t -{ -public: - processor_t(sim_t* _sim, mmu_t* _mmu); - ~processor_t(); - void init(uint32_t _id, icsim_t* defualt_icache, icsim_t* default_dcache); - void step(size_t n, bool noisy); - void deliver_ipi(); - -private: - sim_t* sim; - - // architected state - reg_t XPR[NXPR]; - freg_t FPR[NFPR]; - - // privileged control registers - reg_t pc; - reg_t epc; - reg_t badvaddr; - reg_t cause; - reg_t evec; - reg_t tohost; - reg_t fromhost; - reg_t pcr_k0; - reg_t pcr_k1; - uint32_t id; - uint32_t sr; - uint32_t count; - uint32_t compare; - - bool run; - - // unprivileged control registers - uint32_t fsr; - - // # of bits in an XPR (32 or 64). (redundant with sr) - int xprlen; - - // shared memory - mmu_t& mmu; - - // counters - reg_t cycle; - - // functions - void reset(); - void take_interrupt(); - void set_sr(uint32_t val); - void set_fsr(uint32_t val); - void take_trap(trap_t t, bool noisy); - void disasm(insn_t insn, reg_t pc); - - // vector stuff - void vcfg(); - void setvl(int vlapp); - - reg_t vecbanks; - uint32_t vecbanks_count; - - bool utmode; - int utidx; - int vlmax; - int vl; - int nxfpr_bank; - int nxpr_use; - int nfpr_use; - processor_t* uts[MAX_UTS]; - - // cache sim - icsim_t* icsim; - icsim_t* dcsim; - icsim_t* itlbsim; - icsim_t* dtlbsim; - - friend class sim_t; - friend class mmu_t; - - #include "dispatch.h" -}; - -#endif diff --git a/riscv/riscv-isa-run.cc b/riscv/riscv-isa-run.cc deleted file mode 100644 index bd3b102..0000000 --- a/riscv/riscv-isa-run.cc +++ /dev/null @@ -1,63 +0,0 @@ -#include <unistd.h> -#include <fcntl.h> -#include "common.h" -#include "sim.h" -#include "applink.h" - -int main(int argc, char** argv) -{ - bool debug = false; - int nprocs = 1; - int fromhost_fd = -1, tohost_fd = -1; - size_t icsim_sets = 1024, icsim_linesz = 32, icsim_ways = 1; - - for(int c; (c = getopt(argc,argv,"dp:f:t:i:")) != -1; ) - { - switch(c) - { - case 'd': - debug = true; - break; - case 'p': - nprocs = atoi(optarg); - break; - case 'f': - fromhost_fd = atoi(optarg); - break; - case 't': - tohost_fd = atoi(optarg); - break; - case 'i': - switch(optarg[0]) - { - case 's': - icsim_sets = atoi(optarg+1); - break; - case 'l': - icsim_linesz = atoi(optarg+1); - break; - case 'a': - icsim_ways = atoi(optarg+1); - break; - } - break; - } - } - - demand(fcntl(fromhost_fd,F_GETFD) >= 0, "fromhost file not open"); - demand(fcntl(tohost_fd,F_GETFD) >= 0, "tohost file not open"); - - icsim_t icache(icsim_sets, icsim_ways, icsim_linesz, "I$"); - icsim_t dcache(512, 2, 32, "D$"); - - appserver_link_t applink(tohost_fd, fromhost_fd); - - sim_t s(nprocs, &applink, &icache, &dcache); - try - { - s.run(debug); - } - catch(quit_sim&) - { - } -} diff --git a/riscv/riscv.ac b/riscv/riscv.ac deleted file mode 100644 index 00358fd..0000000 --- a/riscv/riscv.ac +++ /dev/null @@ -1,37 +0,0 @@ -AC_ARG_ENABLE([fpu], AS_HELP_STRING([--disable-fpu], [Disable floating-point])) -AS_IF([test "x$enable_fpu" != "xno"], [ - AC_DEFINE([RISCV_ENABLE_FPU],,[Define if floating-point instructions are supported]) -]) - -AC_ARG_ENABLE([64bit], AS_HELP_STRING([--disable-64bit], [Disable 64-bit mode])) -AS_IF([test "x$enable_64bit" != "xno"], [ - AC_DEFINE([RISCV_ENABLE_64BIT],,[Define if 64-bit mode is supported]) -]) - -AC_ARG_ENABLE([rvc], AS_HELP_STRING([--enable-rvc], [Enable instruction compression])) -AS_IF([test "x$enable_rvc" = "xyes"], [ - AC_DEFINE([RISCV_ENABLE_RVC],,[Define if instruction compression is supported]) -]) - -AC_ARG_ENABLE([vec], AS_HELP_STRING([--disable-vec], [Disable vector processor])) -AS_IF([test "x$enable_vec" != "xno"], [ - AC_DEFINE([RISCV_ENABLE_VEC],,[Define if vector processor is supported]) -]) - -AC_ARG_ENABLE([icsim], AS_HELP_STRING([--enable-icsim], [Enable instruction cache simulator])) -AS_IF([test "x$enable_icsim" = "xyes"], [ - AC_DEFINE([RISCV_ENABLE_ICSIM],,[Define if instruction cache simulator is enabled]) -]) - -libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a -AC_CHECK_FILES([$libopc],[have_libopcodes="yes"],[have_libopcodes="no"]) - -AC_SEARCH_LIBS([bfd_init],[bfd],[],[have_libopcodes="no"]) - -AS_IF([test "$have_libopcodes" = "no"],[ - AC_MSG_WARN([Could not find opcodes library]) - AC_MSG_WARN([Build will not include disassembly support]) -],[ - LIBS="$libopc $LIBS" - AC_DEFINE([RISCV_HAVE_LIBOPCODES],,[Define if libopcodes exists]) -]) diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in deleted file mode 100644 index f075f47..0000000 --- a/riscv/riscv.mk.in +++ /dev/null @@ -1,60 +0,0 @@ -riscv_subproject_deps = \ - softfloat_riscv \ - softfloat \ - -riscv_insn_hdrs := $(notdir $(wildcard $(src_dir)/riscv/insns/*.h)) - -riscv_hdrs = \ - applink.h \ - common.h \ - decode.h \ - mmu.h \ - processor.h \ - sim.h \ - trap.h \ - opcodes.h \ - insn_header.h \ - insn_footer.h \ - dispatch.h \ - -NDISPATCH := 10 -DISPATCH_SRCS := \ - dispatch0.cc \ - dispatch1.cc \ - dispatch2.cc \ - dispatch3.cc \ - dispatch4.cc \ - dispatch5.cc \ - dispatch6.cc \ - dispatch7.cc \ - dispatch8.cc \ - dispatch9.cc \ - dispatch10.cc \ - -$(DISPATCH_SRCS): %.cc: dispatch $(wildcard insns/*.h) $(riscv_hdrs) - $< $(subst dispatch,,$(subst .cc,,$@)) $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@ - -$(src_dir)/riscv/dispatch.h: %.h: dispatch - $< $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@ - -$(patsubst %.h, %.cc, $(riscv_insn_hdrs)): %.cc: insns/%.h $(riscv_hdrs) - @echo \#define FUNC insn_func_$(@:.cc=) > $@ - @echo \#define OPCODE_MASK MASK_$(@:.cc=) >> $@ - @echo \#define OPCODE_MATCH MATCH_$(@:.cc=) >> $@ - @cat $(src_dir)/riscv/insn_header.h >> $@ - @cat $< >> $@ - @cat $(src_dir)/riscv/insn_footer.h >> $@ - -riscv_srcs = \ - applink.cc \ - processor.cc \ - sim.cc \ - trap.cc \ - icsim.cc \ - mmu.cc \ - $(DISPATCH_SRCS) \ - -riscv_test_srcs = - -riscv_install_prog_srcs = \ - riscv-isa-run.cc \ diff --git a/riscv/sim.cc b/riscv/sim.cc deleted file mode 100644 index 9b2677c..0000000 --- a/riscv/sim.cc +++ /dev/null @@ -1,351 +0,0 @@ -#include "sim.h" -#include "applink.h" -#include "common.h" -#include <sys/mman.h> -#include <map> -#include <iostream> -#include <climits> -#include <assert.h> - -sim_t::sim_t(int _nprocs, appserver_link_t* _applink, icsim_t* default_icache, icsim_t* default_dcache) - : applink(_applink), - procs(_nprocs) -{ - size_t memsz0 = sizeof(size_t) == 8 ? 0x100000000ULL : 0x70000000UL; - size_t quantum = std::max(PGSIZE, (reg_t)sysconf(_SC_PAGESIZE)); - memsz0 = memsz0/quantum*quantum; - - memsz = memsz0; - mem = (char*)mmap64(NULL, memsz, PROT_WRITE, MAP_PRIVATE|MAP_ANON, -1, 0); - - if(mem == MAP_FAILED) - { - while(mem == MAP_FAILED && (memsz = memsz*10/11/quantum*quantum)) - mem = (char*)mmap64(NULL, memsz, PROT_WRITE, MAP_PRIVATE|MAP_ANON, -1, 0); - assert(mem != MAP_FAILED); - fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n", - (unsigned long)memsz, (unsigned long)memsz0); - } - - mmu = new mmu_t(mem, memsz); - - for(size_t i = 0; i < num_cores(); i++) - { - procs[i] = new processor_t(this, new mmu_t(mem, memsz)); - procs[i]->init(i, default_icache, default_dcache); - } - - applink->init(this); -} - -sim_t::~sim_t() -{ - for(size_t i = 0; i < num_cores(); i++) - { - mmu_t* pmmu = &procs[i]->mmu; - delete procs[i]; - delete pmmu; - } - delete mmu; - munmap(mem, memsz); -} - -void sim_t::set_tohost(reg_t val) -{ - fromhost = 0; - tohost = val; - applink->wait_for_tohost(); -} - -reg_t sim_t::get_fromhost() -{ - applink->wait_for_fromhost(); - return fromhost; -} - -void sim_t::send_ipi(reg_t who) -{ - if(who < num_cores()) - procs[who]->deliver_ipi(); -} - -void sim_t::run(bool debug) -{ - applink->wait_for_start(); - - // start core 0 - send_ipi(0); - - while(1) - { - if(!debug) - step_all(100,100,false); - else - { - putchar(':'); - char s[128]; - std::cin.getline(s,sizeof(s)-1); - - char* p = strtok(s," "); - if(!p) - { - interactive_run_noisy(std::string("r"), std::vector<std::string>(1,"1")); - continue; - } - std::string cmd = p; - - std::vector<std::string> args; - while((p = strtok(NULL," "))) - args.push_back(p); - - - typedef void (sim_t::*interactive_func)(const std::string&, const std::vector<std::string>&); - std::map<std::string,interactive_func> funcs; - - funcs["r"] = &sim_t::interactive_run_noisy; - funcs["rs"] = &sim_t::interactive_run_silent; - funcs["rp"] = &sim_t::interactive_run_proc_noisy; - funcs["rps"] = &sim_t::interactive_run_proc_silent; - funcs["reg"] = &sim_t::interactive_reg; - funcs["fregs"] = &sim_t::interactive_fregs; - funcs["fregd"] = &sim_t::interactive_fregd; - funcs["mem"] = &sim_t::interactive_mem; - funcs["str"] = &sim_t::interactive_str; - funcs["until"] = &sim_t::interactive_until; - funcs["while"] = &sim_t::interactive_until; - funcs["q"] = &sim_t::interactive_quit; - - try - { - if(funcs.count(cmd)) - (this->*funcs[cmd])(cmd, args); - } - catch(trap_t t) {} - } - } -} - -void sim_t::step_all(size_t n, size_t interleave, bool noisy) -{ - for(size_t j = 0; j < n; j+=interleave) - for(int i = 0; i < (int)num_cores(); i++) - procs[i]->step(interleave,noisy); -} - -void sim_t::interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args) -{ - interactive_run(cmd,args,true); -} - -void sim_t::interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args) -{ - interactive_run(cmd,args,false); -} - -void sim_t::interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy) -{ - if(args.size()) - step_all(atoll(args[0].c_str()),1,noisy); - else - while(1) step_all(1,1,noisy); -} - -void sim_t::interactive_run_proc_noisy(const std::string& cmd, const std::vector<std::string>& args) -{ - interactive_run_proc(cmd,args,true); -} - -void sim_t::interactive_run_proc_silent(const std::string& cmd, const std::vector<std::string>& args) -{ - interactive_run_proc(cmd,args,false); -} - -void sim_t::interactive_run_proc(const std::string& cmd, const std::vector<std::string>& a, bool noisy) -{ - if(a.size() == 0) - return; - - int p = atoi(a[0].c_str()); - if(p >= (int)num_cores()) - return; - - if(a.size() == 2) - procs[p]->step(atoi(a[1].c_str()),noisy); - else - while(1) procs[p]->step(1,noisy); -} - -void sim_t::interactive_quit(const std::string& cmd, const std::vector<std::string>& args) -{ - throw quit_sim(); -} - -reg_t sim_t::get_pc(const std::vector<std::string>& args) -{ - if(args.size() != 1) - throw trap_illegal_instruction; - - int p = atoi(args[0].c_str()); - if(p >= (int)num_cores()) - throw trap_illegal_instruction; - - return procs[p]->pc; -} - -reg_t sim_t::get_reg(const std::vector<std::string>& args) -{ - if(args.size() != 2) - throw trap_illegal_instruction; - - int p = atoi(args[0].c_str()); - int r = atoi(args[1].c_str()); - if(p >= (int)num_cores() || r >= NXPR) - throw trap_illegal_instruction; - - return procs[p]->XPR[r]; -} - -reg_t sim_t::get_freg(const std::vector<std::string>& args) -{ - if(args.size() != 2) - throw trap_illegal_instruction; - - int p = atoi(args[0].c_str()); - int r = atoi(args[1].c_str()); - if(p >= (int)num_cores() || r >= NFPR) - throw trap_illegal_instruction; - - return procs[p]->FPR[r]; -} - -reg_t sim_t::get_tohost(const std::vector<std::string>& args) -{ - if(args.size() != 1) - throw trap_illegal_instruction; - - int p = atoi(args[0].c_str()); - if(p >= (int)num_cores()) - throw trap_illegal_instruction; - - return procs[p]->tohost; -} - -void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::string>& args) -{ - printf("0x%016llx\n",(unsigned long long)get_reg(args)); -} - -union fpr -{ - reg_t r; - float s; - double d; -}; - -void sim_t::interactive_fregs(const std::string& cmd, const std::vector<std::string>& args) -{ - fpr f; - f.r = get_freg(args); - printf("%g\n",f.s); -} - -void sim_t::interactive_fregd(const std::string& cmd, const std::vector<std::string>& args) -{ - fpr f; - f.r = get_freg(args); - printf("%g\n",f.d); -} - -reg_t sim_t::get_mem(const std::vector<std::string>& args) -{ - if(args.size() != 1 && args.size() != 2) - throw trap_illegal_instruction; - - std::string addr_str = args[0]; - if(args.size() == 2) - { - int p = atoi(args[0].c_str()); - if(p >= (int)num_cores()) - throw trap_illegal_instruction; - mmu->set_vm_enabled(!!(procs[p]->sr & SR_VM)); - mmu->set_ptbr(procs[p]->mmu.get_ptbr()); - addr_str = args[1]; - } - - reg_t addr = strtol(addr_str.c_str(),NULL,16), val; - if(addr == LONG_MAX) - addr = strtoul(addr_str.c_str(),NULL,16); - - switch(addr % 8) - { - case 0: - val = mmu->load_uint64(addr); - break; - case 4: - val = mmu->load_uint32(addr); - break; - case 2: - case 6: - val = mmu->load_uint16(addr); - break; - default: - val = mmu->load_uint8(addr); - break; - } - return val; -} - -void sim_t::interactive_mem(const std::string& cmd, const std::vector<std::string>& args) -{ - printf("0x%016llx\n",(unsigned long long)get_mem(args)); -} - -void sim_t::interactive_str(const std::string& cmd, const std::vector<std::string>& args) -{ - if(args.size() != 1) - throw trap_illegal_instruction; - - reg_t addr = strtol(args[0].c_str(),NULL,16); - - char ch; - while((ch = mmu->load_uint8(addr++))) - putchar(ch); - - putchar('\n'); -} - -void sim_t::interactive_until(const std::string& cmd, const std::vector<std::string>& args) -{ - if(args.size() < 3) - return; - - std::string scmd = args[0]; - reg_t val = strtol(args[args.size()-1].c_str(),NULL,16); - if(val == LONG_MAX) - val = strtoul(args[args.size()-1].c_str(),NULL,16); - - std::vector<std::string> args2; - args2 = std::vector<std::string>(args.begin()+1,args.end()-1); - - while(1) - { - reg_t current; - if(scmd == "reg") - current = get_reg(args2); - else if(scmd == "pc") - current = get_pc(args2); - else if(scmd == "mem") - current = get_mem(args2); - else if(scmd == "tohost") - current = get_tohost(args2); - else - return; - - if(cmd == "until" && current == val) - break; - if(cmd == "while" && current != val) - break; - - step_all(1,1,false); - } -} diff --git a/riscv/sim.h b/riscv/sim.h deleted file mode 100644 index ab388b8..0000000 --- a/riscv/sim.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef _RISCV_SIM_H -#define _RISCV_SIM_H - -#include <vector> -#include <string> -#include "processor.h" -#include "mmu.h" - -class appserver_link_t; - -class sim_t -{ -public: - sim_t(int _nprocs, appserver_link_t* _applink, icsim_t* _default_icache, icsim_t* default_dcache); - ~sim_t(); - void run(bool debug); - - void set_tohost(reg_t val); - reg_t get_fromhost(); - void send_ipi(reg_t who); - - size_t num_cores() { return procs.size(); } - -private: - // global architected state - reg_t tohost; - reg_t fromhost; - - appserver_link_t* applink; - - size_t memsz; - char* mem; - mmu_t* mmu; - std::vector<processor_t*> procs; - - void step_all(size_t n, size_t interleave, bool noisy); - - void interactive_quit(const std::string& cmd, const std::vector<std::string>& args); - - void interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy); - void interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args); - void interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args); - - void interactive_run_proc(const std::string& cmd, const std::vector<std::string>& args, bool noisy); - void interactive_run_proc_noisy(const std::string& cmd, const std::vector<std::string>& args); - void interactive_run_proc_silent(const std::string& cmd, const std::vector<std::string>& args); - - void interactive_reg(const std::string& cmd, const std::vector<std::string>& args); - void interactive_fregs(const std::string& cmd, const std::vector<std::string>& args); - void interactive_fregd(const std::string& cmd, const std::vector<std::string>& args); - void interactive_mem(const std::string& cmd, const std::vector<std::string>& args); - void interactive_str(const std::string& cmd, const std::vector<std::string>& args); - void interactive_until(const std::string& cmd, const std::vector<std::string>& args); - - reg_t get_reg(const std::vector<std::string>& args); - reg_t get_freg(const std::vector<std::string>& args); - reg_t get_mem(const std::vector<std::string>& args); - reg_t get_pc(const std::vector<std::string>& args); - reg_t get_tohost(const std::vector<std::string>& args); - - friend class appserver_link_t; -}; - -struct quit_sim {}; - -#endif diff --git a/riscv/trap.cc b/riscv/trap.cc deleted file mode 100644 index cdf7b8d..0000000 --- a/riscv/trap.cc +++ /dev/null @@ -1,10 +0,0 @@ -#include "trap.h" - -const char* trap_name(trap_t t) -{ - #undef DECLARE_TRAP - #define DECLARE_TRAP(x) "trap_"#x - static const char* names[] = { TRAP_LIST }; - - return (unsigned)t >= sizeof(names)/sizeof(names[0]) ? "unknown" : names[t]; -} diff --git a/riscv/trap.h b/riscv/trap.h deleted file mode 100644 index 12a1c04..0000000 --- a/riscv/trap.h +++ /dev/null @@ -1,43 +0,0 @@ -#ifndef _RISCV_TRAP_H -#define _RISCV_TRAP_H - -#define TRAP_LIST \ - DECLARE_TRAP(instruction_address_misaligned), \ - DECLARE_TRAP(instruction_access_fault), \ - DECLARE_TRAP(illegal_instruction), \ - DECLARE_TRAP(privileged_instruction), \ - DECLARE_TRAP(fp_disabled), \ - DECLARE_TRAP(interrupt), \ - DECLARE_TRAP(syscall), \ - DECLARE_TRAP(breakpoint), \ - DECLARE_TRAP(load_address_misaligned), \ - DECLARE_TRAP(store_address_misaligned), \ - DECLARE_TRAP(load_access_fault), \ - DECLARE_TRAP(store_access_fault), \ - DECLARE_TRAP(vector_disabled), \ - DECLARE_TRAP(vector_bank), \ - DECLARE_TRAP(vector_illegal_instruction), \ - DECLARE_TRAP(reserved1), \ - DECLARE_TRAP(reserved2), \ - DECLARE_TRAP(reserved3), \ - DECLARE_TRAP(int0), \ - DECLARE_TRAP(int1), \ - DECLARE_TRAP(int2), \ - DECLARE_TRAP(int3), \ - DECLARE_TRAP(int4), \ - DECLARE_TRAP(int5), \ - DECLARE_TRAP(int6), \ - DECLARE_TRAP(int7), \ - -#define DECLARE_TRAP(x) trap_##x -enum trap_t -{ - TRAP_LIST - NUM_TRAPS -}; - -struct halt_t {}; // thrown to stop the processor from running - -extern "C" const char* trap_name(trap_t t); - -#endif |