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author | Scott Johnson <scott.johnson@arilinc.com> | 2022-07-18 07:00:45 -0700 |
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committer | Scott Johnson <scott.johnson@arilinc.com> | 2022-07-18 07:00:47 -0700 |
commit | f0d84787423ef5a0329bb79c45775dbc7ec16de5 (patch) | |
tree | 86725ec491fc5a107ceea82f9dd926f117f9e076 /riscv | |
parent | a2697ac775dac31e0aabf0223171b1e2f8a7fcde (diff) | |
download | riscv-isa-sim-f0d84787423ef5a0329bb79c45775dbc7ec16de5.zip riscv-isa-sim-f0d84787423ef5a0329bb79c45775dbc7ec16de5.tar.gz riscv-isa-sim-f0d84787423ef5a0329bb79c45775dbc7ec16de5.tar.bz2 |
Remove no-longer-necessary typecast
It was previously necessary because we were shifting left before
assigning to a reg_t, but that changed in the previous commit.
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/mmu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index f652bf8..fdc641f 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -58,7 +58,7 @@ public: reg_t res = 0; for (size_t i = 0; i < size; i++) { const reg_t byteaddr = addr + (target_big_endian? size-1-i : i); - const reg_t bytedata = (reg_t)load_uint8(byteaddr); + const reg_t bytedata = load_uint8(byteaddr); res += bytedata << (i * 8); } return res; |