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author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-05-09 23:33:04 +0200 |
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committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-05-09 23:34:17 +0200 |
commit | d6731d58d43cbfd239f249803dc928d98fd996ca (patch) | |
tree | 2be596a6368d75ce31f56598e6504c22a3ca84c2 /riscv | |
parent | 8dd8f11510a33ada2c93d9071aecd33615445f5b (diff) | |
download | riscv-isa-sim-d6731d58d43cbfd239f249803dc928d98fd996ca.zip riscv-isa-sim-d6731d58d43cbfd239f249803dc928d98fd996ca.tar.gz riscv-isa-sim-d6731d58d43cbfd239f249803dc928d98fd996ca.tar.bz2 |
Zfa: fix exception behaviour for fcvtmod.w.d
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/insns/fcvtmod_w_d.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/riscv/insns/fcvtmod_w_d.h b/riscv/insns/fcvtmod_w_d.h index 89b9b95..e39400d 100644 --- a/riscv/insns/fcvtmod_w_d.h +++ b/riscv/insns/fcvtmod_w_d.h @@ -38,12 +38,14 @@ if (exp == 0) { } else { /* The fraction is shifted out entirely. */ frac = 0; + inexact = true; } - /* Notice overflow or inexact exceptions. */ + /* Handle overflows */ if (true_exp > 31 || frac > (sign ? 0x80000000ull : 0x7fffffff)) { /* Overflow, for which this operation raises invalid. */ invalid = true; + inexact = false; /* invalid takes precedence */ } /* Honor the sign. */ |