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| author | Andrew Waterman <andrew@sifive.com> | 2022-12-14 04:46:16 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-12-14 04:46:16 -0800 |
| commit | d00c01d2af6c141c0a9147533323582e6491e9c3 (patch) | |
| tree | 7a365ecbfe4bf92aa6f25d210ba29c51909025c2 /riscv | |
| parent | 291188f59cfd84873c5b85e015eb79345406389a (diff) | |
| parent | f1c0a947be9988a48b33535b80e2e4a1ecf5965f (diff) | |
| download | riscv-isa-sim-d00c01d2af6c141c0a9147533323582e6491e9c3.zip riscv-isa-sim-d00c01d2af6c141c0a9147533323582e6491e9c3.tar.gz riscv-isa-sim-d00c01d2af6c141c0a9147533323582e6491e9c3.tar.bz2 | |
Merge pull request #1175 from riscv-software-src/fix-mac-build
Fix build on M1
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/vector_unit.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/vector_unit.cc b/riscv/vector_unit.cc index 17c63a9..c5e51bd 100644 --- a/riscv/vector_unit.cc +++ b/riscv/vector_unit.cc @@ -92,6 +92,7 @@ template signed char& vectorUnit_t::elt<signed char>(reg_t, reg_t, bool); template short& vectorUnit_t::elt<short>(reg_t, reg_t, bool); template int& vectorUnit_t::elt<int>(reg_t, reg_t, bool); template long& vectorUnit_t::elt<long>(reg_t, reg_t, bool); +template long long& vectorUnit_t::elt<long long>(reg_t, reg_t, bool); template uint8_t& vectorUnit_t::elt<uint8_t>(reg_t, reg_t, bool); template uint16_t& vectorUnit_t::elt<uint16_t>(reg_t, reg_t, bool); template uint32_t& vectorUnit_t::elt<uint32_t>(reg_t, reg_t, bool); |