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| author | YenHaoChen <howard25336284@gmail.com> | 2022-11-29 15:14:45 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2022-11-30 12:11:42 +0800 |
| commit | b3ab18867eacbe28cb9c6435d065d01cc704b5d7 (patch) | |
| tree | fe4393b06a8bf9ed660363ce43c058f42bbdeea0 /riscv | |
| parent | 97e7887de530a86ba76f944a53c80915766c5c15 (diff) | |
| download | riscv-isa-sim-b3ab18867eacbe28cb9c6435d065d01cc704b5d7.zip riscv-isa-sim-b3ab18867eacbe28cb9c6435d065d01cc704b5d7.tar.gz riscv-isa-sim-b3ab18867eacbe28cb9c6435d065d01cc704b5d7.tar.bz2 | |
triggers: mcontrol does not support VS and VU modes
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/triggers.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 763a2d5..eb35d02 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -101,7 +101,8 @@ match_result_t mcontrol_t::memory_access_match(processor_t * const proc, operati (operation == triggers::OPERATION_LOAD && !load) || (state->prv == PRV_M && !m) || (state->prv == PRV_S && !s) || - (state->prv == PRV_U && !u)) { + (state->prv == PRV_U && !u) || + (state->v)) { return match_result_t(false); } |