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| author | Andrew Waterman <andrew@sifive.com> | 2024-07-04 08:52:41 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-07-04 08:52:41 -0700 |
| commit | 98d2c29e431f3b14feefbda48c5f70c2f451acf2 (patch) | |
| tree | 8d5c266c8f3475709998d39ee021f03fbc9408c5 /riscv | |
| parent | 4a2da916671d49d9ab82f702f50995c19110c2a3 (diff) | |
| parent | 952b98fd8b0f915e8a5eb6f0df8dcc3fdfd56c8c (diff) | |
| download | riscv-isa-sim-98d2c29e431f3b14feefbda48c5f70c2f451acf2.zip riscv-isa-sim-98d2c29e431f3b14feefbda48c5f70c2f451acf2.tar.gz riscv-isa-sim-98d2c29e431f3b14feefbda48c5f70c2f451acf2.tar.bz2 | |
Merge pull request #1717 from riscv-software-src/fix-ss-load
Loads to shadow-stack pages are allowed
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index d10e23a..8acbc2b 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -557,7 +557,7 @@ reg_t mmu_t::walk(mem_access_info_t access_info) // shadow stack access cause store access fault if xwr!=010 and xwr!=001 throw trap_store_access_fault(virt, addr, 0, 0); } else if (type == FETCH || hlvx ? !(pte & PTE_X) : - type == LOAD ? !(pte & PTE_R) && !(mxr && (pte & PTE_X)) : + type == LOAD ? !(pte & PTE_R) && !(sse && (pte & PTE_W)) && !(mxr && (pte & PTE_X)) : !(pte & PTE_W)) { break; } else if ((ppn & ((reg_t(1) << ptshift) - 1)) != 0) { |