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| author | Dave.Wen <dave.wen@sifive.com> | 2020-12-07 00:27:48 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-12-14 02:10:20 -0800 |
| commit | 9224c93cc09c68171cb9a9804751387d0d065aff (patch) | |
| tree | 3a176bf815897015e3570a2e5a5700d489a082ba /riscv | |
| parent | e88a30c22957c2b75be8d6a0c69c3122d3d60b85 (diff) | |
| download | riscv-isa-sim-9224c93cc09c68171cb9a9804751387d0d065aff.zip riscv-isa-sim-9224c93cc09c68171cb9a9804751387d0d065aff.tar.gz riscv-isa-sim-9224c93cc09c68171cb9a9804751387d0d065aff.tar.bz2 | |
rvv: fix the v[z|s]ext about elmul checking.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/decode.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 97018a3..b69416a 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1865,7 +1865,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ require_vm; \ reg_t from = P.VU.vsew / div; \ require(from >= e8 && from <= e64); \ - require(((float)P.VU.vflmul / div) >= ((float)P.VU.vsew_min / P.VU.ELEN)); \ + require(((float)P.VU.vflmul / div) >= 0.125 && ((float)P.VU.vflmul / div) <= 8 ); \ require_align(insn.rd(), P.VU.vflmul); \ require_align(insn.rs2(), P.VU.vflmul / div); \ if ((P.VU.vflmul / div) < 1) { \ |