diff options
| author | YenHaoChen <howard25336284@gmail.com> | 2022-11-29 09:47:56 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2022-11-30 12:11:42 +0800 |
| commit | 8b7e11ff04260cb451ba5b081a8ff70a59a0c3f2 (patch) | |
| tree | 3140c56aa1b6bb6f5c0dc9c3d98c9e3d6cc501cd /riscv | |
| parent | 07530cb3c5c60c854cfb7377a3b9d1fe2b50297d (diff) | |
| download | riscv-isa-sim-8b7e11ff04260cb451ba5b081a8ff70a59a0c3f2.zip riscv-isa-sim-8b7e11ff04260cb451ba5b081a8ff70a59a0c3f2.tar.gz riscv-isa-sim-8b7e11ff04260cb451ba5b081a8ff70a59a0c3f2.tar.bz2 | |
triggers: refactor: remove obsolete checking of debug_mode in disabled_trigger_t::tdata1_write()
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/triggers.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 11f79ee..8c494c3 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -26,7 +26,7 @@ void disabled_trigger_t::tdata1_write(processor_t * const proc, const reg_t val) { // Any supported tdata.type results in disabled trigger auto xlen = proc->get_xlen(); - dmode = proc->get_state()->debug_mode ? get_field(val, CSR_TDATA1_DMODE(xlen)) : 0; + dmode = get_field(val, CSR_TDATA1_DMODE(xlen)); } reg_t mcontrol_t::tdata1_read(const processor_t * const proc) const noexcept { |