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author | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-01 10:08:16 -0700 |
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committer | Andrew Waterman <aswaterman@gmail.com> | 2021-09-08 07:59:02 -0700 |
commit | 3d21672de4cba853ce441767b3a24ffec8e8c782 (patch) | |
tree | 6536f2db4982249c0d3ece461b43c60ea830ec82 /riscv | |
parent | dc7dfc7015dfa983e62f8ad0aa1d0f4accc7e500 (diff) | |
download | riscv-isa-sim-3d21672de4cba853ce441767b3a24ffec8e8c782.zip riscv-isa-sim-3d21672de4cba853ce441767b3a24ffec8e8c782.tar.gz riscv-isa-sim-3d21672de4cba853ce441767b3a24ffec8e8c782.tar.bz2 |
Simplify calculation of mxr
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/mmu.cc | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 7f2858c..b50ca8c 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -347,9 +347,7 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode, bool virt, bool hlvx bool s_mode = mode == PRV_S; bool sum = proc->state.sstatus->readvirt(virt) & MSTATUS_SUM; - reg_t arch_vsstatus = proc->state.sstatus->readvirt(true); - reg_t arch_sstatus = proc->state.sstatus->readvirt(false); - bool mxr = (arch_sstatus | (virt ? arch_vsstatus : 0)) & MSTATUS_MXR; + bool mxr = (proc->state.sstatus->readvirt(false) | proc->state.sstatus->readvirt(virt)) & MSTATUS_MXR; // verify bits xlen-1:va_bits-1 are all equal int va_bits = PGSHIFT + vm.levels * vm.idxbits; |