diff options
| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-09-08 21:16:35 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-09-08 22:11:59 +0800 |
| commit | d85446f81f3c9405a2041ab5235281a3bbaab77f (patch) | |
| tree | 561932297c74a43f7f9be8e465e836b06a071b4c /riscv/v_ext_macros.h | |
| parent | 3721abe667842a47c7b0447399fb59e1cb46f696 (diff) | |
| download | riscv-isa-sim-d85446f81f3c9405a2041ab5235281a3bbaab77f.zip riscv-isa-sim-d85446f81f3c9405a2041ab5235281a3bbaab77f.tar.gz riscv-isa-sim-d85446f81f3c9405a2041ab5235281a3bbaab77f.tar.bz2 | |
Remove unnecessary argument alu(always false) from macro
require_vector_novtype
Diffstat (limited to 'riscv/v_ext_macros.h')
| -rw-r--r-- | riscv/v_ext_macros.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index 71a5401..2893306 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -1317,7 +1317,7 @@ reg_t index[P.VU.vlmax]; \ p->VU.vstart->write(0); #define VI_LD_WHOLE(elt_width) \ - require_vector_novtype(true, false); \ + require_vector_novtype(true); \ require(sizeof(elt_width ## _t) * 8 <= P.VU.ELEN); \ const reg_t baseAddr = RS1; \ const reg_t vd = insn.rd(); \ @@ -1349,7 +1349,7 @@ reg_t index[P.VU.vlmax]; \ P.VU.vstart->write(0); #define VI_ST_WHOLE \ - require_vector_novtype(true, false); \ + require_vector_novtype(true); \ const reg_t baseAddr = RS1; \ const reg_t vs3 = insn.rd(); \ const reg_t len = insn.v_nf() + 1; \ |