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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-09-08 21:04:42 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-09-08 21:04:42 +0800 |
| commit | 3721abe667842a47c7b0447399fb59e1cb46f696 (patch) | |
| tree | 3cd43e5f740f1bae8ee1f5262252fc0b15f8672e /riscv/v_ext_macros.h | |
| parent | 2437a717c89e9efa5e28c0370c94c1c257f5f910 (diff) | |
| download | riscv-isa-sim-3721abe667842a47c7b0447399fb59e1cb46f696.zip riscv-isa-sim-3721abe667842a47c7b0447399fb59e1cb46f696.tar.gz riscv-isa-sim-3721abe667842a47c7b0447399fb59e1cb46f696.tar.bz2 | |
Remove redundant require_vector in macro VI_MERGE_LOOP_BASE
require_vector is also included in VI_GENERAL_LOOP_BASE
Diffstat (limited to 'riscv/v_ext_macros.h')
| -rw-r--r-- | riscv/v_ext_macros.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index 3f9b4af..71a5401 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -517,7 +517,6 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) bool use_first = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1; #define VI_MERGE_LOOP_BASE \ - require_vector(true); \ VI_GENERAL_LOOP_BASE \ VI_MERGE_VARS |