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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-04-14 22:49:24 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-05-29 09:01:21 +0800 |
| commit | 48f66191758f3bca04e6d7e85348f266df148c14 (patch) | |
| tree | 0fb6548e20dbb276210b1515d232bcd7fa5eebe0 /riscv/v_ext_macros.h | |
| parent | 8aacc4effde92122a25beadac594162187767d7e (diff) | |
| download | riscv-isa-sim-48f66191758f3bca04e6d7e85348f266df148c14.zip riscv-isa-sim-48f66191758f3bca04e6d7e85348f266df148c14.tar.gz riscv-isa-sim-48f66191758f3bca04e6d7e85348f266df148c14.tar.bz2 | |
Add support for new instructions of Zvfbfwma extension
Diffstat (limited to 'riscv/v_ext_macros.h')
| -rw-r--r-- | riscv/v_ext_macros.h | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index 376c330..41256c7 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -1488,11 +1488,27 @@ reg_t index[P.VU.vlmax]; \ reg_t UNUSED rs2_num = insn.rs2(); \ softfloat_roundingMode = STATE.frm->read(); +#define VI_VFP_BF16_COMMON \ + require_fp; \ + require((P.VU.vsew == e16 && p->extension_enabled(EXT_ZVFBFWMA))); \ + require_vector(true); \ + require(STATE.frm->read() < 0x5); \ + reg_t UNUSED vl = P.VU.vl->read(); \ + reg_t UNUSED rd_num = insn.rd(); \ + reg_t UNUSED rs1_num = insn.rs1(); \ + reg_t UNUSED rs2_num = insn.rs2(); \ + softfloat_roundingMode = STATE.frm->read(); + #define VI_VFP_LOOP_BASE \ VI_VFP_COMMON \ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ VI_LOOP_ELEMENT_SKIP(); +#define VI_VFP_BF16_LOOP_BASE \ + VI_VFP_BF16_COMMON \ + for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ + VI_LOOP_ELEMENT_SKIP(); + #define VI_VFP_LOOP_CMP_BASE \ VI_VFP_COMMON \ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ @@ -1818,6 +1834,25 @@ reg_t index[P.VU.vlmax]; \ DEBUG_RVV_FP_VV; \ VI_VFP_LOOP_END +#define VI_VFP_BF16_VF_LOOP_WIDE(BODY) \ + VI_CHECK_DSS(false); \ + VI_VFP_BF16_LOOP_BASE \ + switch (P.VU.vsew) { \ + case e16: { \ + float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \ + float32_t vs2 = bf16_to_f32(P.VU.elt<bfloat16_t>(rs2_num, i)); \ + float32_t rs1 = bf16_to_f32(FRS1_BF); \ + BODY; \ + set_fp_exceptions; \ + break; \ + } \ + default: \ + require(0); \ + break; \ + }; \ + DEBUG_RVV_FP_VV; \ + VI_VFP_LOOP_END + #define VI_VFP_VV_LOOP_WIDE(BODY16, BODY32) \ VI_CHECK_DSS(true); \ VI_VFP_LOOP_BASE \ @@ -1845,6 +1880,25 @@ reg_t index[P.VU.vlmax]; \ DEBUG_RVV_FP_VV; \ VI_VFP_LOOP_END +#define VI_VFP_BF16_VV_LOOP_WIDE(BODY) \ + VI_CHECK_DSS(true); \ + VI_VFP_BF16_LOOP_BASE \ + switch (P.VU.vsew) { \ + case e16: { \ + float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \ + float32_t vs2 = bf16_to_f32(P.VU.elt<bfloat16_t>(rs2_num, i)); \ + float32_t vs1 = bf16_to_f32(P.VU.elt<bfloat16_t>(rs1_num, i)); \ + BODY; \ + set_fp_exceptions; \ + break; \ + } \ + default: \ + require(0); \ + break; \ + }; \ + DEBUG_RVV_FP_VV; \ + VI_VFP_LOOP_END + #define VI_VFP_WF_LOOP_WIDE(BODY16, BODY32) \ VI_CHECK_DDS(false); \ VI_VFP_LOOP_BASE \ |