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author | YenHaoChen <39526191+YenHaoChen@users.noreply.github.com> | 2022-10-26 08:36:48 +0800 |
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committer | Tim Newsome <tim@sifive.com> | 2022-11-15 10:49:09 -0800 |
commit | 388753f9412d95d83d909b1f0447b8b0ad1ffd6b (patch) | |
tree | b69f867bb19c797d86f07778ca414947a0980885 /riscv/triggers.cc | |
parent | 07e3d415c5c28d505882fe81f568d6d278520ee5 (diff) | |
download | riscv-isa-sim-itrigger-etrigger-cleanup.zip riscv-isa-sim-itrigger-etrigger-cleanup.tar.gz riscv-isa-sim-itrigger-etrigger-cleanup.tar.bz2 |
Use ACTION_DEBUG_MODE instead of 1itrigger-etrigger-cleanup
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
Diffstat (limited to 'riscv/triggers.cc')
-rw-r--r-- | riscv/triggers.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 1e3c2bb..824aa4a 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -233,7 +233,7 @@ bool etrigger_t::tdata1_write(processor_t * const proc, const reg_t val) noexcep s = proc->extension_enabled('S') ? get_field(val, CSR_ETRIGGER_S) : 0; u = proc->extension_enabled('U') ? get_field(val, CSR_ETRIGGER_U) : 0; action = (action_t)get_field(val, CSR_ETRIGGER_ACTION); - if (action > 4 || (action==1 && dmode==0)) + if (action > 4 || (action==ACTION_DEBUG_MODE && dmode==0)) action = ACTION_DEBUG_EXCEPTION; return true; } |