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| author | Jerry Zhao <jerryz123@berkeley.edu> | 2022-12-13 16:51:45 -0800 |
|---|---|---|
| committer | Jerry Zhao <jerryz123@berkeley.edu> | 2022-12-15 14:02:40 -0800 |
| commit | 9f93b98c87cfdbcbeb59b9da298344c840f747a4 (patch) | |
| tree | 3ba6d247ca03596c7a9b9ab7ed93957a69b33c6d /riscv/processor.cc | |
| parent | 4d4159e76d61980e300cea7bdbdab873f07db12a (diff) | |
| download | riscv-isa-sim-9f93b98c87cfdbcbeb59b9da298344c840f747a4.zip riscv-isa-sim-9f93b98c87cfdbcbeb59b9da298344c840f747a4.tar.gz riscv-isa-sim-9f93b98c87cfdbcbeb59b9da298344c840f747a4.tar.bz2 | |
Rename memif_endianness_t to endianness_t
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 8ca3bb7..560f71e 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -30,7 +30,7 @@ processor_t::processor_t(const isa_parser_t *isa, const char* varch, simif_t* sim, uint32_t id, bool halt_on_reset, - memif_endianness_t endianness, + endianness_t endianness, FILE* log_file, std::ostream& sout_) : debug(false), halt_request(HR_NONE), isa(isa), sim(sim), id(id), xlen(0), histogram_enabled(false), log_commits_enabled(false), |