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author | Andrew Waterman <andrew@sifive.com> | 2022-10-05 17:21:11 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2022-10-05 17:21:19 -0700 |
commit | d7edd7ac550dab81b84f2001793e04b663330658 (patch) | |
tree | d7b5e21c4acf4cf09fcfdd22a6c9b38b0460ef9b /riscv/mmu.cc | |
parent | cb7e6b840be13ebc46fdcdb23df6db61ff306fde (diff) | |
download | riscv-isa-sim-d7edd7ac550dab81b84f2001793e04b663330658.zip riscv-isa-sim-d7edd7ac550dab81b84f2001793e04b663330658.tar.gz riscv-isa-sim-d7edd7ac550dab81b84f2001793e04b663330658.tar.bz2 |
Remove unused variable to fix build
Diffstat (limited to 'riscv/mmu.cc')
-rw-r--r-- | riscv/mmu.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 367c859..38a7241 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -142,7 +142,6 @@ bool mmu_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes) void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate_flags) { if (!matched_trigger) { - reg_t data = reg_from_bytes(len, bytes); matched_trigger = trigger_exception(triggers::OPERATION_LOAD, addr, false); if (matched_trigger) throw *matched_trigger; |