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author | YenHaoChen <howard25336284@gmail.com> | 2022-11-30 09:39:07 +0800 |
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committer | YenHaoChen <howard25336284@gmail.com> | 2022-12-01 09:39:49 +0800 |
commit | bbaad7a422198d616e72331d7274dbb9aa9cde9f (patch) | |
tree | 23e3c7cb503fd8f47143da7345f1beade2cbebf8 /riscv/mmu.cc | |
parent | 8da8a8c89a937eb4e97fa1158deda84721b5900a (diff) | |
download | riscv-isa-sim-bbaad7a422198d616e72331d7274dbb9aa9cde9f.zip riscv-isa-sim-bbaad7a422198d616e72331d7274dbb9aa9cde9f.tar.gz riscv-isa-sim-bbaad7a422198d616e72331d7274dbb9aa9cde9f.tar.bz2 |
triggers: refactor: rename memory_access_match() to detect_memory_access_match()
Diffstat (limited to 'riscv/mmu.cc')
-rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 86022e3..e4fba3d 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -157,7 +157,7 @@ void mmu_t::check_triggers(triggers::operation_t operation, reg_t address, std:: if (matched_trigger || !proc) return; - triggers::match_result_t match = proc->TM.memory_access_match(operation, address, data); + triggers::match_result_t match = proc->TM.detect_memory_access_match(operation, address, data); if (match.fire) switch (match.timing) { |