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| author | Jerry Zhao <jerryz123@berkeley.edu> | 2022-10-25 11:37:44 -0700 |
|---|---|---|
| committer | Jerry Zhao <jerryz123@berkeley.edu> | 2022-10-25 11:49:33 -0700 |
| commit | b265325d19fe9eb9145c65fe110735ff03c1b90c (patch) | |
| tree | 5d1826b2eb8f1e0af019c7d1f833880da256f26a /riscv/mmu.cc | |
| parent | cefccba8cf1008691a1bb5d36bd318e281ffc635 (diff) | |
| download | riscv-isa-sim-b265325d19fe9eb9145c65fe110735ff03c1b90c.zip riscv-isa-sim-b265325d19fe9eb9145c65fe110735ff03c1b90c.tar.gz riscv-isa-sim-b265325d19fe9eb9145c65fe110735ff03c1b90c.tar.bz2 | |
Remove set_target_endianness | add --big-endian flag
Set target endianess in constructors
Diffstat (limited to 'riscv/mmu.cc')
| -rw-r--r-- | riscv/mmu.cc | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 3f9b5e9..a966180 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -5,16 +5,19 @@ #include "simif.h" #include "processor.h" -mmu_t::mmu_t(simif_t* sim, processor_t* proc) +mmu_t::mmu_t(simif_t* sim, memif_endianness_t endianness, processor_t* proc) : sim(sim), proc(proc), #ifdef RISCV_ENABLE_DUAL_ENDIAN - target_big_endian(false), + target_big_endian(endianness == memif_endianness_big), #endif check_triggers_fetch(false), check_triggers_load(false), check_triggers_store(false), matched_trigger(NULL) { +#ifndef RISCV_ENABLE_DUAL_ENDIAN + assert(endianness == memif_endianness_little); +#endif flush_tlb(); yield_load_reservation(); } |