diff options
| author | Andrew Waterman <andrew@sifive.com> | 2022-10-19 17:28:37 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-19 21:12:25 -0700 |
| commit | a09b88d4abb8fe3015c3921c7468e78b7f09da15 (patch) | |
| tree | fb0e7f7986ac20104289e2f2e412b77fcaaea25a /riscv/mmu.cc | |
| parent | 905db657f56c86b5fb558e7a3a5ea04dafa46858 (diff) | |
| download | riscv-isa-sim-a09b88d4abb8fe3015c3921c7468e78b7f09da15.zip riscv-isa-sim-a09b88d4abb8fe3015c3921c7468e78b7f09da15.tar.gz riscv-isa-sim-a09b88d4abb8fe3015c3921c7468e78b7f09da15.tar.bz2 | |
Remove require_alignment flag from loads
The last remaining use was LR, which we can identify through other means.
Diffstat (limited to 'riscv/mmu.cc')
| -rw-r--r-- | riscv/mmu.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 0c858ae..3f9b5e9 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -199,7 +199,7 @@ void mmu_t::load_slow_path_intrapage(reg_t addr, reg_t len, uint8_t* bytes, uint } } -void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate_flags, bool UNUSED require_alignment) +void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate_flags) { check_triggers(triggers::OPERATION_LOAD, addr); @@ -210,7 +210,7 @@ void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate #ifndef RISCV_ENABLE_MISALIGNED throw trap_load_address_misaligned(gva, addr, 0, 0); #else - if (require_alignment) + if (xlate_flags & RISCV_XLATE_LR) throw trap_load_access_fault(gva, addr, 0, 0); reg_t len_page0 = std::min(len, PGSIZE - addr % PGSIZE); |