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| author | Tim Newsome <tim@sifive.com> | 2021-04-27 11:44:54 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-04-27 11:44:54 -0700 |
| commit | 3bda10daab79b0922abd5b0fff0396defa44e5e1 (patch) | |
| tree | d0ccfbb4ffc76a1ebc3acedd3e9086f3a73c8aa4 /riscv/jtag_dtm.h | |
| parent | 9d4f45c2ebf105503974fc80a42590ca1584c354 (diff) | |
| download | riscv-isa-sim-3bda10daab79b0922abd5b0fff0396defa44e5e1.zip riscv-isa-sim-3bda10daab79b0922abd5b0fff0396defa44e5e1.tar.gz riscv-isa-sim-3bda10daab79b0922abd5b0fff0396defa44e5e1.tar.bz2 | |
Implement JTAG BYPASS register. (#697)
* Implement JTAG BYPASS register.
This allows spike to put into a virtual scan chain with other
remote_bitbang JTAG devices.
* Initialize bypass to 0.
Also change what we do on what edge. In theory that's more correct but
in practice it doesn't make a difference.
Diffstat (limited to 'riscv/jtag_dtm.h')
| -rw-r--r-- | riscv/jtag_dtm.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/jtag_dtm.h b/riscv/jtag_dtm.h index 3482b8a..23a54be 100644 --- a/riscv/jtag_dtm.h +++ b/riscv/jtag_dtm.h @@ -54,6 +54,7 @@ class jtag_dtm_t const unsigned abits = 6; uint32_t dtmcontrol; uint64_t dmi; + unsigned bypass; // Number of Run-Test/Idle cycles needed before we call this access // complete. unsigned rti_remaining; |