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| author | emelcher <elmar@dsc.ufcg.edu.br> | 2021-04-13 20:11:02 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-04-13 16:11:02 -0700 |
| commit | 9d4f45c2ebf105503974fc80a42590ca1584c354 (patch) | |
| tree | 1e219fc4512a173442310410ab49a5d02105c94c /riscv/jtag_dtm.h | |
| parent | 6c18ef569c210daf9713b4f26bc0c4f2c3769457 (diff) | |
| download | riscv-isa-sim-9d4f45c2ebf105503974fc80a42590ca1584c354.zip riscv-isa-sim-9d4f45c2ebf105503974fc80a42590ca1584c354.tar.gz riscv-isa-sim-9d4f45c2ebf105503974fc80a42590ca1584c354.tar.bz2 | |
Display 32 bits (#693)
* make value display depend on max_xlen
* try to make spike look for correct pk
* PRIx64 instead of PRIx32, TARGET_ARCH back to 64
* 32 bit memory data, exception epc and tval
Diffstat (limited to 'riscv/jtag_dtm.h')
0 files changed, 0 insertions, 0 deletions