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| author | Andrew Waterman <andrew@sifive.com> | 2026-02-25 22:45:34 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-02-25 22:45:34 -0800 |
| commit | 591cff16109ced6a21bb2a612a3853b4e9cbd86d (patch) | |
| tree | 78ec9949e3beb269dc587cbab69ba0f859897181 /riscv/insns/vmsof_m.h | |
| parent | ae1531c207eccfe11d6009d39ab7998a93dfb139 (diff) | |
| parent | a437348306077d0ee26353faba73a8b639ece2a2 (diff) | |
| download | riscv-isa-sim-master.zip riscv-isa-sim-master.tar.gz riscv-isa-sim-master.tar.bz2 | |
Only set mstatus.VS for legal vector instructions
Diffstat (limited to 'riscv/insns/vmsof_m.h')
| -rw-r--r-- | riscv/insns/vmsof_m.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/insns/vmsof_m.h b/riscv/insns/vmsof_m.h index 5753dbf..caaff04 100644 --- a/riscv/insns/vmsof_m.h +++ b/riscv/insns/vmsof_m.h @@ -24,3 +24,5 @@ for (reg_t i = P.VU.vstart->read() ; i < vl; ++i) { P.VU.set_mask_elt(rd_num, i, res); } } + +VECTOR_END; |