Merge pull request #2207 from riscv-software-src/fix-2206HEADmaster

Only set mstatus.VS for legal vector instructions

27 files changed, 44 insertions, 7 deletions

diff --git a/riscv/insns/vcompress_vm.h b/riscv/insns/vcompress_vm.h
index 6624d8b..8754eb0 100644
--- a/riscv/insns/vcompress_vm.h
+++ b/riscv/insns/vcompress_vm.h
@@ -27,4 +27,5 @@ VI_GENERAL_LOOP_BASE
 
     ++pos;
   }
-VI_LOOP_END_BASE;
+
+VI_LOOP_END;
diff --git a/riscv/insns/vcpop_m.h b/riscv/insns/vcpop_m.h
index 26a1276..260f45d 100644
--- a/riscv/insns/vcpop_m.h
+++ b/riscv/insns/vcpop_m.h
@@ -10,3 +10,5 @@ for (reg_t i=P.VU.vstart->read(); i<vl; ++i) {
   popcount += vs2_bit && (insn.v_vm() || P.VU.mask_elt(0, i));
 }
 WRITE_RD(popcount);
+
+VECTOR_END;
diff --git a/riscv/insns/vfbdot_vv.h b/riscv/insns/vfbdot_vv.h
index 8d4c792..b70e309 100644
--- a/riscv/insns/vfbdot_vv.h
+++ b/riscv/insns/vfbdot_vv.h
@@ -14,3 +14,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;
diff --git a/riscv/insns/vfirst_m.h b/riscv/insns/vfirst_m.h
index e3f5263..261ea5a 100644
--- a/riscv/insns/vfirst_m.h
+++ b/riscv/insns/vfirst_m.h
@@ -14,3 +14,5 @@ for (reg_t i=P.VU.vstart->read(); i < vl; ++i) {
   }
 }
 WRITE_RD(pos);
+
+VECTOR_END;
diff --git a/riscv/insns/vfmv_f_s.h b/riscv/insns/vfmv_f_s.h
index 65a3cff..f4e984e 100644
--- a/riscv/insns/vfmv_f_s.h
+++ b/riscv/insns/vfmv_f_s.h
@@ -29,4 +29,4 @@ if (FLEN == 64) {
   WRITE_FRD(f32(vs2_0));
 }
 
-P.VU.vstart->write(0);
+VECTOR_END;
diff --git a/riscv/insns/vfmv_s_f.h b/riscv/insns/vfmv_s_f.h
index 917948d..11975f2 100644
--- a/riscv/insns/vfmv_s_f.h
+++ b/riscv/insns/vfmv_s_f.h
@@ -21,4 +21,4 @@ if (vl > 0 && P.VU.vstart->read() < vl) {
       break;
   }
 }
-P.VU.vstart->write(0);
+VECTOR_END;
diff --git a/riscv/insns/vfqbdot_alt_vv.h b/riscv/insns/vfqbdot_alt_vv.h
index f1df781..dcdcb11 100644
--- a/riscv/insns/vfqbdot_alt_vv.h
+++ b/riscv/insns/vfqbdot_alt_vv.h
@@ -15,3 +15,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;
diff --git a/riscv/insns/vfqbdot_vv.h b/riscv/insns/vfqbdot_vv.h
index fe3e652..b4fdffe 100644
--- a/riscv/insns/vfqbdot_vv.h
+++ b/riscv/insns/vfqbdot_vv.h
@@ -15,3 +15,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;
diff --git a/riscv/insns/vfqldot_alt_vv.h b/riscv/insns/vfqldot_alt_vv.h
index ea18828..a2b7fd2 100644
--- a/riscv/insns/vfqldot_alt_vv.h
+++ b/riscv/insns/vfqldot_alt_vv.h
@@ -15,3 +15,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;
diff --git a/riscv/insns/vfqldot_vv.h b/riscv/insns/vfqldot_vv.h
index b03ec29..ca46d26 100644
--- a/riscv/insns/vfqldot_vv.h
+++ b/riscv/insns/vfqldot_vv.h
@@ -15,3 +15,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;
diff --git a/riscv/insns/vfwbdot_vv.h b/riscv/insns/vfwbdot_vv.h
index b8d35a7..47f7c9b 100644
--- a/riscv/insns/vfwbdot_vv.h
+++ b/riscv/insns/vfwbdot_vv.h
@@ -13,3 +13,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;
diff --git a/riscv/insns/vfwldot_vv.h b/riscv/insns/vfwldot_vv.h
index 63a4e47..fe1cf09 100644
--- a/riscv/insns/vfwldot_vv.h
+++ b/riscv/insns/vfwldot_vv.h
@@ -13,3 +13,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;
diff --git a/riscv/insns/vid_v.h b/riscv/insns/vid_v.h
index 510132d..ad7da21 100644
--- a/riscv/insns/vid_v.h
+++ b/riscv/insns/vid_v.h
@@ -25,4 +25,4 @@ for (reg_t i = P.VU.vstart->read() ; i < P.VU.vl->read(); ++i) {
   }
 }
 
-P.VU.vstart->write(0);
+VECTOR_END;
diff --git a/riscv/insns/viota_m.h b/riscv/insns/viota_m.h
index 00155db..4a67769 100644
--- a/riscv/insns/viota_m.h
+++ b/riscv/insns/viota_m.h
@@ -45,3 +45,4 @@ for (reg_t i = 0; i < vl; ++i) {
   }
 }
 
+VECTOR_END;
diff --git a/riscv/insns/vmsbf_m.h b/riscv/insns/vmsbf_m.h
index 3f736e0..7c907a6 100644
--- a/riscv/insns/vmsbf_m.h
+++ b/riscv/insns/vmsbf_m.h
@@ -25,3 +25,5 @@ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) {
     P.VU.set_mask_elt(rd_num, i, res);
   }
 }
+
+VECTOR_END;
diff --git a/riscv/insns/vmsif_m.h b/riscv/insns/vmsif_m.h
index b029327..7d98655 100644
--- a/riscv/insns/vmsif_m.h
+++ b/riscv/insns/vmsif_m.h
@@ -26,3 +26,5 @@ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) {
     P.VU.set_mask_elt(rd_num, i, res);
   }
 }
+
+VECTOR_END;
diff --git a/riscv/insns/vmsof_m.h b/riscv/insns/vmsof_m.h
index 5753dbf..caaff04 100644
--- a/riscv/insns/vmsof_m.h
+++ b/riscv/insns/vmsof_m.h
@@ -24,3 +24,5 @@ for (reg_t i = P.VU.vstart->read() ; i < vl; ++i) {
     P.VU.set_mask_elt(rd_num, i, res);
   }
 }
+
+VECTOR_END;
diff --git a/riscv/insns/vmv_s_x.h b/riscv/insns/vmv_s_x.h
index 23a6b56..bd848a8 100644
--- a/riscv/insns/vmv_s_x.h
+++ b/riscv/insns/vmv_s_x.h
@@ -26,4 +26,4 @@ if (vl > 0 && P.VU.vstart->read() < vl) {
   vl = 0;
 }
 
-P.VU.vstart->write(0);
+VECTOR_END;
diff --git a/riscv/insns/vmv_x_s.h b/riscv/insns/vmv_x_s.h
index 57a9e1a..c28dbf4 100644
--- a/riscv/insns/vmv_x_s.h
+++ b/riscv/insns/vmv_x_s.h
@@ -24,4 +24,4 @@ default:
 
 WRITE_RD(sext_xlen(res));
 
-P.VU.vstart->write(0);
+VECTOR_END;
diff --git a/riscv/insns/vmvnfr_v.h b/riscv/insns/vmvnfr_v.h
index 9c52810..fa47bb6 100644
--- a/riscv/insns/vmvnfr_v.h
+++ b/riscv/insns/vmvnfr_v.h
@@ -24,4 +24,4 @@ if (vd != vs2 && start < size) {
   }
 }
 
-P.VU.vstart->write(0);
+VECTOR_END;
diff --git a/riscv/insns/vqbdots_vv.h b/riscv/insns/vqbdots_vv.h
index 55c3dd2..de34835 100644
--- a/riscv/insns/vqbdots_vv.h
+++ b/riscv/insns/vqbdots_vv.h
@@ -21,3 +21,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;
diff --git a/riscv/insns/vqbdotu_vv.h b/riscv/insns/vqbdotu_vv.h
index a73d568..8eee3a9 100644
--- a/riscv/insns/vqbdotu_vv.h
+++ b/riscv/insns/vqbdotu_vv.h
@@ -21,3 +21,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;
diff --git a/riscv/insns/vqldots_vv.h b/riscv/insns/vqldots_vv.h
index ce6376a..bde2296 100644
--- a/riscv/insns/vqldots_vv.h
+++ b/riscv/insns/vqldots_vv.h
@@ -21,3 +21,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;
diff --git a/riscv/insns/vqldotu_vv.h b/riscv/insns/vqldotu_vv.h
index 2b674b1..cd3691a 100644
--- a/riscv/insns/vqldotu_vv.h
+++ b/riscv/insns/vqldotu_vv.h
@@ -21,3 +21,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;
diff --git a/riscv/insns/vsetivli.h b/riscv/insns/vsetivli.h
index f880e96..f30564f 100644
--- a/riscv/insns/vsetivli.h
+++ b/riscv/insns/vsetivli.h
@@ -1,2 +1,3 @@
 require_vector_novtype(false);
 WRITE_RD(P.VU.set_vl(insn.rd(), -1, insn.rs1(), insn.v_zimm10()));
+VECTOR_END;
diff --git a/riscv/insns/vsetvl.h b/riscv/insns/vsetvl.h
index 4d03542..f18d5be 100644
--- a/riscv/insns/vsetvl.h
+++ b/riscv/insns/vsetvl.h
@@ -1,2 +1,3 @@
 require_vector_novtype(false);
 WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, RS2));
+VECTOR_END;
diff --git a/riscv/insns/vsetvli.h b/riscv/insns/vsetvli.h
index d1f43b5..140cc30 100644
--- a/riscv/insns/vsetvli.h
+++ b/riscv/insns/vsetvli.h
@@ -1,2 +1,3 @@
 require_vector_novtype(false);
 WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, insn.v_zimm11()));
+VECTOR_END;