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| author | Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU> | 2010-11-05 14:06:12 -0700 |
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| committer | Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU> | 2010-11-21 16:54:33 -0800 |
| commit | 7471eee0ba7d80c83048cbbf47d7837f586b9264 (patch) | |
| tree | 09c1b60abf1fe766cfe748c9bd7b5c301f4f177b /riscv/insns/mfcr.h | |
| parent | 3f144b12ed35f7fee4c7faf937e144807acb1e2b (diff) | |
| download | riscv-isa-sim-7471eee0ba7d80c83048cbbf47d7837f586b9264.zip riscv-isa-sim-7471eee0ba7d80c83048cbbf47d7837f586b9264.tar.gz riscv-isa-sim-7471eee0ba7d80c83048cbbf47d7837f586b9264.tar.bz2 | |
[xcc, sim, pk, opcodes] new instruction encoding!
Diffstat (limited to 'riscv/insns/mfcr.h')
| -rw-r--r-- | riscv/insns/mfcr.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/mfcr.h b/riscv/insns/mfcr.h index 1c7ec2d..78b71d0 100644 --- a/riscv/insns/mfcr.h +++ b/riscv/insns/mfcr.h @@ -14,4 +14,4 @@ switch(insn.rtype.rs2) val = -1; } -RDR = gprlen == 64 ? val : sext32(val); +RD = gprlen == 64 ? val : sext32(val); |