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| author | Christian Herber <christian.herber@oss.nxp.com> | 2024-06-10 16:48:27 +0200 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-06-13 16:26:46 -0700 |
| commit | 70d26d64e6ba2da329357a88dc313277fff6c22c (patch) | |
| tree | e528fe302700c53397c51319fdc65e59c9ac1ffd /riscv/insns/ld.h | |
| parent | 62d5c06dfb3aae38d979afc066bd604cbccbfbe0 (diff) | |
| download | riscv-isa-sim-70d26d64e6ba2da329357a88dc313277fff6c22c.zip riscv-isa-sim-70d26d64e6ba2da329357a88dc313277fff6c22c.tar.gz riscv-isa-sim-70d26d64e6ba2da329357a88dc313277fff6c22c.tar.bz2 | |
Adding Zilsd and Zcmlsd extensions (Load/store pair for RV32)
Diffstat (limited to 'riscv/insns/ld.h')
| -rw-r--r-- | riscv/insns/ld.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h index 3dea301..cb0399b 100644 --- a/riscv/insns/ld.h +++ b/riscv/insns/ld.h @@ -1,2 +1,8 @@ -require_rv64; -WRITE_RD(MMU.load<int64_t>(RS1 + insn.i_imm())); +require((xlen == 64) || p->extension_enabled(EXT_ZILSD)); + +if (xlen == 32) { + WRITE_RD_PAIR(MMU.load<int64_t>(RS1 + insn.i_imm())); +} else { + WRITE_RD(MMU.load<int64_t>(RS1 + insn.i_imm())); +} + |