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| author | YenHaoChen <howard25336284@gmail.com> | 2023-07-17 12:27:59 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2023-07-25 08:41:17 +0800 |
| commit | e7e188011182a60c94bf2b35c94f02795d906da4 (patch) | |
| tree | 6771c1375002a61bde53f11e5cf039e49eedef4c /riscv/csrs.h | |
| parent | 7f22022e1ad4019afb18e48ceb76ec9e6f483b50 (diff) | |
| download | riscv-isa-sim-e7e188011182a60c94bf2b35c94f02795d906da4.zip riscv-isa-sim-e7e188011182a60c94bf2b35c94f02795d906da4.tar.gz riscv-isa-sim-e7e188011182a60c94bf2b35c94f02795d906da4.tar.bz2 | |
legalize henvcfg.CBIE
The value 2 of henvcfg.CBIE is reserved. This commit legalizes it to 0.
Reference: https://github.com/riscv/riscv-CMOs/issues/65
Diffstat (limited to 'riscv/csrs.h')
| -rw-r--r-- | riscv/csrs.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/csrs.h b/riscv/csrs.h index f08262b..e483ea3 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -468,7 +468,7 @@ class envcfg_csr_t: public masked_csr_t { // henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0 // henvcfg.stce is read_only 0 when menvcfg.stce = 0 // henvcfg.hade is read_only 0 when menvcfg.hade = 0 -class henvcfg_csr_t final: public masked_csr_t { +class henvcfg_csr_t final: public envcfg_csr_t { public: henvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init, csr_t_p menvcfg); |