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author | Ming-Yi Lai <ming-yi.lai@mediatek.com> | 2024-01-04 16:49:22 +0800 |
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committer | Ming-Yi Lai <ming-yi.lai@mediatek.com> | 2024-03-06 17:21:00 +0800 |
commit | 194dfb1d5b84e12b9400729fac27560eceaf6b0d (patch) | |
tree | e7986eae737b357096e29949b77a9cdd98160cb4 /riscv/csrs.h | |
parent | 0172240f7e1404c4dd4e6d05731c2c91bfec016a (diff) | |
download | riscv-isa-sim-194dfb1d5b84e12b9400729fac27560eceaf6b0d.zip riscv-isa-sim-194dfb1d5b84e12b9400729fac27560eceaf6b0d.tar.gz riscv-isa-sim-194dfb1d5b84e12b9400729fac27560eceaf6b0d.tar.bz2 |
Zicfilp: Add CSR fields
Diffstat (limited to 'riscv/csrs.h')
-rw-r--r-- | riscv/csrs.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/riscv/csrs.h b/riscv/csrs.h index b3dfe1c..a472801 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -21,6 +21,11 @@ class processor_t; struct state_t; +enum struct elp_t { + NO_LP_EXPECTED = 0, + LP_EXPECTED = 1, +}; + // Parent, abstract class for all CSRs class csr_t { public: @@ -690,6 +695,7 @@ class dcsr_csr_t: public csr_t { bool halt; bool v; uint8_t cause; + elp_t pelp; }; typedef std::shared_ptr<dcsr_csr_t> dcsr_csr_t_p; |