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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-15 10:39:01 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-15 10:39:01 +0800 |
| commit | 72250c8628fb05a02f77f6500ded658575b0a561 (patch) | |
| tree | d3195483f2bd0aa911e18c891dabf4d027db037f /riscv/csrs.cc | |
| parent | d90f290f55e6281af0f48c3bc1e637b011fbe53d (diff) | |
| download | riscv-isa-sim-72250c8628fb05a02f77f6500ded658575b0a561.zip riscv-isa-sim-72250c8628fb05a02f77f6500ded658575b0a561.tar.gz riscv-isa-sim-72250c8628fb05a02f77f6500ded658575b0a561.tar.bz2 | |
Disable Zvfh{min} when misa.V is cleared
Diffstat (limited to 'riscv/csrs.cc')
| -rw-r--r-- | riscv/csrs.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 9dd4123..923a13c 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -642,6 +642,8 @@ bool misa_csr_t::unlogged_write(const reg_t val) noexcept { proc->set_extension_enable(EXT_ZCMT, proc->extension_enabled(EXT_ZCA)); proc->set_extension_enable(EXT_ZFH, new_misa & (1L << ('F' - 'A'))); proc->set_extension_enable(EXT_ZFHMIN, new_misa & (1L << ('F' - 'A'))); + proc->set_extension_enable(EXT_ZVFH, new_misa & (1L << ('V' - 'A'))); + proc->set_extension_enable(EXT_ZVFHMIN, new_misa & (1L << ('V' - 'A'))); // update the hypervisor-only bits in MEDELEG and other CSRs if (!new_h && prev_h) { |