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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-15 10:37:15 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-15 10:37:15 +0800 |
| commit | d90f290f55e6281af0f48c3bc1e637b011fbe53d (patch) | |
| tree | 847e8ea41597a923d1610557eeff74edbc3736bf /riscv/csrs.cc | |
| parent | 0e4f928b3cf53b323ccb5064f3f7d58d351a3060 (diff) | |
| download | riscv-isa-sim-d90f290f55e6281af0f48c3bc1e637b011fbe53d.zip riscv-isa-sim-d90f290f55e6281af0f48c3bc1e637b011fbe53d.tar.gz riscv-isa-sim-d90f290f55e6281af0f48c3bc1e637b011fbe53d.tar.bz2 | |
Disable Zfh{min} when misa.F is cleared
Diffstat (limited to 'riscv/csrs.cc')
| -rw-r--r-- | riscv/csrs.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index a5eec56..9dd4123 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -640,6 +640,8 @@ bool misa_csr_t::unlogged_write(const reg_t val) noexcept { proc->set_extension_enable(EXT_ZCB, proc->extension_enabled(EXT_ZCA)); proc->set_extension_enable(EXT_ZCMP, proc->extension_enabled(EXT_ZCA)); proc->set_extension_enable(EXT_ZCMT, proc->extension_enabled(EXT_ZCA)); + proc->set_extension_enable(EXT_ZFH, new_misa & (1L << ('F' - 'A'))); + proc->set_extension_enable(EXT_ZFHMIN, new_misa & (1L << ('F' - 'A'))); // update the hypervisor-only bits in MEDELEG and other CSRs if (!new_h && prev_h) { |