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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-15 10:41:51 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-15 10:42:10 +0800 |
| commit | 32168de8ea2251a26ac2634c2c1add4492cb43cb (patch) | |
| tree | 91af922161127923df05630b45365f6c26e98249 /riscv/csrs.cc | |
| parent | 72250c8628fb05a02f77f6500ded658575b0a561 (diff) | |
| download | riscv-isa-sim-32168de8ea2251a26ac2634c2c1add4492cb43cb.zip riscv-isa-sim-32168de8ea2251a26ac2634c2c1add4492cb43cb.tar.gz riscv-isa-sim-32168de8ea2251a26ac2634c2c1add4492cb43cb.tar.bz2 | |
Disable Zvfh when Zfhmin is disabled
Diffstat (limited to 'riscv/csrs.cc')
| -rw-r--r-- | riscv/csrs.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 923a13c..5cadfbe 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -642,7 +642,7 @@ bool misa_csr_t::unlogged_write(const reg_t val) noexcept { proc->set_extension_enable(EXT_ZCMT, proc->extension_enabled(EXT_ZCA)); proc->set_extension_enable(EXT_ZFH, new_misa & (1L << ('F' - 'A'))); proc->set_extension_enable(EXT_ZFHMIN, new_misa & (1L << ('F' - 'A'))); - proc->set_extension_enable(EXT_ZVFH, new_misa & (1L << ('V' - 'A'))); + proc->set_extension_enable(EXT_ZVFH, (new_misa & (1L << ('V' - 'A'))) && proc->extension_enabled(EXT_ZFHMIN)); proc->set_extension_enable(EXT_ZVFHMIN, new_misa & (1L << ('V' - 'A'))); // update the hypervisor-only bits in MEDELEG and other CSRs |