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| author | Andrew Waterman <andrew@sifive.com> | 2024-03-22 14:00:26 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-03-22 14:00:26 -0700 |
| commit | 534fe05b836d7420ae45c2b2faaf27891d20b50b (patch) | |
| tree | 50e0ce6b30a561e37e4dd968149fc0dfc15b0982 | |
| parent | 2e86ec4b83c2fe3eb19669244357d288be8b45fa (diff) | |
| parent | cbeded947ec4acaa76a091dc839557d52f96a4ce (diff) | |
| download | riscv-isa-sim-534fe05b836d7420ae45c2b2faaf27891d20b50b.zip riscv-isa-sim-534fe05b836d7420ae45c2b2faaf27891d20b50b.tar.gz riscv-isa-sim-534fe05b836d7420ae45c2b2faaf27891d20b50b.tar.bz2 | |
Merge pull request #1630 from mylai-mtk/zicfilp
Allow software check exception to be delegated from M mode regardless of Zicfilp being enabled
| -rw-r--r-- | riscv/csrs.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index b1f4b7d..4900581 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -906,7 +906,7 @@ bool medeleg_csr_t::unlogged_write(const reg_t val) noexcept { | (1 << CAUSE_LOAD_PAGE_FAULT) | (1 << CAUSE_STORE_PAGE_FAULT) | (proc->extension_enabled('H') ? hypervisor_exceptions : 0) - | (proc->extension_enabled(EXT_ZICFILP) ? (1 << CAUSE_SOFTWARE_CHECK_FAULT) : 0) + | (1 << CAUSE_SOFTWARE_CHECK_FAULT) ; return basic_csr_t::unlogged_write((read() & ~mask) | (val & mask)); } |