diff options
author | Andrew Waterman <andrew@sifive.com> | 2024-04-08 18:46:02 -0700 |
---|---|---|
committer | GitHub <noreply@github.com> | 2024-04-08 18:46:02 -0700 |
commit | 4196bc8fafadb643671a0d92a7b32ac84457dc8d (patch) | |
tree | 8a57198d32c410f260650a17ffb9c87cb62e5209 | |
parent | 3427b459f88d2334368a1abbdf5a3000957f08e8 (diff) | |
parent | a101bfebe07c92447b8239737c1a18702e63df98 (diff) | |
download | riscv-isa-sim-4196bc8fafadb643671a0d92a7b32ac84457dc8d.zip riscv-isa-sim-4196bc8fafadb643671a0d92a7b32ac84457dc8d.tar.gz riscv-isa-sim-4196bc8fafadb643671a0d92a7b32ac84457dc8d.tar.bz2 |
Merge pull request #1640 from YenHaoChen/pr-henvcfg
Ignore writes to henvcfg fields (PBMTE, STCE, and ADUE) when read-only 0
-rw-r--r-- | riscv/csrs.cc | 5 | ||||
-rw-r--r-- | riscv/csrs.h | 3 |
2 files changed, 8 insertions, 0 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 4900581..4a612e5 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1549,6 +1549,11 @@ void henvcfg_csr_t::verify_permissions(insn_t insn, bool write) const { masked_csr_t::verify_permissions(insn, write); } +bool henvcfg_csr_t::unlogged_write(const reg_t val) noexcept { + const reg_t mask = menvcfg->read() | ~(MENVCFG_PBMTE | MENVCFG_STCE | MENVCFG_ADUE); + return envcfg_csr_t::unlogged_write((masked_csr_t::read() & ~mask) | (val & mask)); +} + stimecmp_csr_t::stimecmp_csr_t(processor_t* const proc, const reg_t addr, const reg_t imask): basic_csr_t(proc, addr, 0), intr_mask(imask) { } diff --git a/riscv/csrs.h b/riscv/csrs.h index 990c301..2595243 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -490,6 +490,9 @@ class henvcfg_csr_t final: public envcfg_csr_t { virtual void verify_permissions(insn_t insn, bool write) const override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + private: csr_t_p menvcfg; }; |