aboutsummaryrefslogtreecommitdiff
BranchCommit messageAuthorAge
device_flagsAllow device flags after --device cmdline argJerry Zhao11 months
dts_parsingSupport parsing procs fully from DTSJerry Zhao5 months
dynamicbuild: Dynamically link installed progsJerry Zhao16 months
force-rttibuild: Include all symbols from extension.o when linking spike's mainJerry Zhao16 months
log-commits-fastertmpAndrew Waterman12 months
masterMerge pull request #1859 from ved-rivos/issue_1857Andrew Waterman44 hours
nolibfdtRemove in-tree libfdt, rely on system-installed libfdtJerry Zhao11 months
rivosinc-etrigger_fix_exception_matchCall stash_privilege more selectivelyAndrew Waterman18 months
speed2Split off opcode_cache_entry_tJerry Zhao11 days
whole-archivebuild: Link spike binaries with --whole-archiveJerry Zhao16 months
[...]
 
TagDownloadAuthorAge
dummy-tag-for-ci-storageriscv-isa-sim-dummy-tag-for-ci-storage.zip  riscv-isa-sim-dummy-tag-for-ci-storage.tar.gz  riscv-isa-sim-dummy-tag-for-ci-storage.tar.bz2  Andrew Waterman2 years
v1.1.0riscv-isa-sim-1.1.0.zip  riscv-isa-sim-1.1.0.tar.gz  riscv-isa-sim-1.1.0.tar.bz2  Andrew Waterman3 years
v1.0.0riscv-isa-sim-1.0.0.zip  riscv-isa-sim-1.0.0.tar.gz  riscv-isa-sim-1.0.0.tar.bz2  Andrew Waterman6 years
 
AgeCommit messageAuthorFilesLines
2017-05-25minNum -> minimumNumberpriv-1.10Andrew Waterman4-8/+16
2017-05-13Make C.LI/C.LUI trapping behavior match specAndrew Waterman2-2/+1
2017-05-05UXL=SXL=MXLAndrew Waterman2-4/+18
2017-05-05Trap superpage PTEs when PPN LSBs are setAndrew Waterman1-0/+2
2017-05-01Fix segfault when accessing bad memory addressesAndrew Waterman3-11/+8
2017-05-01Set default entry point from ELFAndrew Waterman3-6/+10
2017-04-30Add option to set start pcAndrew Waterman3-26/+24
2017-04-30Support more flexible main memory allocationAndrew Waterman5-35/+113
2017-04-30Store both host & target address in soft TLBAndrew Waterman3-38/+47
2017-04-25FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.XAndrew Waterman5-10/+10
[...]
generated by cgit v1.1 at 2024-11-16 10:22:43 +0000