index
:
rocket-tools/riscv-isa-sim.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
Branch
Commit message
Author
Age
device_flags
Allow device flags after --device cmdline arg
Jerry Zhao
10 months
dts_parsing
Support parsing procs fully from DTS
Jerry Zhao
3 months
dynamic
build: Dynamically link installed progs
Jerry Zhao
15 months
fix-bf16
Add f64_to_bf16; fix f32_to_bf16
Andrew Waterman
18 months
force-rtti
build: Include all symbols from extension.o when linking spike's main
Jerry Zhao
15 months
log-commits-faster
tmp
Andrew Waterman
11 months
master
Merge pull request #1829 from NXP/update-zilsd-to-v0.10
Andrew Waterman
8 days
nolibfdt
Remove in-tree libfdt, rely on system-installed libfdt
Jerry Zhao
10 months
rivosinc-etrigger_fix_exception_match
Call stash_privilege more selectively
Andrew Waterman
17 months
whole-archive
build: Link spike binaries with --whole-archive
Jerry Zhao
15 months
[...]
Tag
Download
Author
Age
dummy-tag-for-ci-storage
riscv-isa-sim-dummy-tag-for-ci-storage.zip
riscv-isa-sim-dummy-tag-for-ci-storage.tar.gz
riscv-isa-sim-dummy-tag-for-ci-storage.tar.bz2
Andrew Waterman
2 years
v1.1.0
riscv-isa-sim-1.1.0.zip
riscv-isa-sim-1.1.0.tar.gz
riscv-isa-sim-1.1.0.tar.bz2
Andrew Waterman
3 years
v1.0.0
riscv-isa-sim-1.0.0.zip
riscv-isa-sim-1.0.0.tar.gz
riscv-isa-sim-1.0.0.tar.bz2
Andrew Waterman
6 years
Age
Commit message
Author
Files
Lines
2020-07-31
add configurable LR/SC reservation set
load_reservation_set_size
Udit Khanna
7
-11
/
+95
2020-07-30
Merge pull request #519 from chihminchao/rvv-pre-1.0
Andrew Waterman
64
-282
/
+483
2020-07-29
f16: fix Nan-Box macro
Chih-Min Chao
1
-1
/
+1
2020-07-29
rvv: fix frac_lmul get function
Chih-Min Chao
1
-1
/
+1
2020-07-29
rvv: remove isa string zvamoand zvlsseg
Chih-Min Chao
3
-18
/
+0
2020-07-29
rvv: remove veew/vemul state
Chih-Min Chao
3
-32
/
+25
2020-07-29
rvv: add vrgatherei16.vv
Chih-Min Chao
4
-13
/
+51
2020-07-29
rvv: add new whole reg load/store instructions
Chih-Min Chao
25
-23
/
+212
2020-07-29
rvv: op: rearrange some instruction since generation order change
Chih-Min Chao
1
-36
/
+36
2020-07-29
rvv: op: fix amo naming
Chih-Min Chao
39
-148
/
+148
[...]