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BranchCommit messageAuthorAge
device_flagsAllow device flags after --device cmdline argJerry Zhao9 months
dts_parsingSupport parsing procs fully from DTSJerry Zhao2 months
dynamicbuild: Dynamically link installed progsJerry Zhao14 months
fix-bf16Add f64_to_bf16; fix f32_to_bf16Andrew Waterman17 months
force-rttibuild: Include all symbols from extension.o when linking spike's mainJerry Zhao14 months
log-commits-fastertmpAndrew Waterman10 months
masterMerge pull request #1797 from YenHaoChen/pr-vectorAndrew Waterman7 days
nolibfdtRemove in-tree libfdt, rely on system-installed libfdtJerry Zhao9 months
rivosinc-etrigger_fix_exception_matchCall stash_privilege more selectivelyAndrew Waterman16 months
whole-archivebuild: Link spike binaries with --whole-archiveJerry Zhao14 months
[...]
 
TagDownloadAuthorAge
dummy-tag-for-ci-storageriscv-isa-sim-dummy-tag-for-ci-storage.zip  riscv-isa-sim-dummy-tag-for-ci-storage.tar.gz  riscv-isa-sim-dummy-tag-for-ci-storage.tar.bz2  Andrew Waterman24 months
v1.1.0riscv-isa-sim-1.1.0.zip  riscv-isa-sim-1.1.0.tar.gz  riscv-isa-sim-1.1.0.tar.bz2  Andrew Waterman3 years
v1.0.0riscv-isa-sim-1.0.0.zip  riscv-isa-sim-1.0.0.tar.gz  riscv-isa-sim-1.0.0.tar.bz2  Andrew Waterman5 years
 
AgeCommit messageAuthorFilesLines
2013-11-29Remove debug printf in vsetprecconfprecQuan Nguyen1-1/+0
2013-11-29Add vsetprec instruction prototypeQuan Nguyen5-0/+17
2013-11-24Merge branch 'master' of github.com:ucb-bar/riscv-isa-sim into HEADQuan Nguyen7-4/+9
2013-11-21fix slli/slliw encoding bugYunsup Lee2-4/+4
2013-11-05add accelerator disabled causeYunsup Lee1-0/+1
2013-11-05correctly trap when SR_EA is disabledYunsup Lee4-0/+4
2013-11-04Fix declaration of half-precision instructionsAlbert Ou2-0/+2
2013-11-04Re-add Hwacha header fileAlbert Ou1-0/+1
2013-11-04Implement "half-baked" half-precision instruction subset for HwachaAlbert Ou39-2/+336
2013-11-04Merge branch 'master' of github.com:ucb-bar/riscv-isa-sim into confprecAlbert Ou30-180/+463
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