aboutsummaryrefslogtreecommitdiff
path: root/riscv
AgeCommit message (Expand)AuthorFilesLines
2020-05-18rvv: fix unit/strided load/store checking ruleChih-Min Chao1-29/+18
2020-05-18rvv: vid's mlen overlap checkingDave.Wen1-1/+1
2020-05-18rvv: MLEN=1 overlappingDave.Wen1-4/+4
2020-05-17rvv: mlen=1 WIPDave.Wen2-4/+5
2020-05-14rvv: amo: only allow 32/64 bit elementChih-Min Chao2-16/+1
2020-05-14rvv: add vzext/vsextChih-Min Chao8-0/+44
2020-05-14rvv: op: reorder vextChih-Min Chao1-18/+18
2020-05-14rvv: dont't explicit throw exceptionChih-Min Chao1-1/+1
2020-05-14rvv: fix the fractional lmulDave.Wen2-8/+19
2020-05-13rvv: wrong operation to the fractional LMUL bitDave.Wen1-1/+1
2020-05-13rvv: amo: fix wrong index eewChih-Min Chao27-27/+27
2020-05-13rvv: change to 0.9amoChih-Min Chao48-83/+218
2020-05-13rvv: amo pre-0.9Chih-Min Chao13-0/+89
2020-05-13rvv: fractional_lmul when lmul < 1Dave.Wen4-10/+20
2020-05-13vtype: fix the vta and vma functions and debugging displayDave.Wen3-3/+6
2020-05-13eew: add eewDave.Wen1-8/+17
2020-05-13eew: fix the eew=0 caseDave.Wen2-13/+18
2020-05-12rvv: add ext opcodeChih-Min Chao1-0/+18
2020-05-12rvv: op: change vfunary0 and funary1 func6 fieldChih-Min Chao1-47/+47
2020-05-12rvv: ldst: add missng check for VI_LDChih-Min Chao1-2/+1
2020-05-11rvv: change to 0.9 ldstChih-Min Chao78-451/+638
2020-05-07rvv: add eew and lmul for vle/vse/vleffDave.Wen4-7/+39
2020-05-06fractional_lmul: update the vtype register and alos remove the useless reg_maskDave.Wen1-1/+3
2020-05-04zfh: implementation all instructionsChih-Min Chao37-0/+206
2020-05-04zfh: op: add scalar opcodeChih-Min Chao1-0/+108
2020-04-29zfh: zfh require F extension supportChih-Min Chao1-0/+3
2020-04-27rvv: align VCSR with upstreamChih-Min Chao2-15/+13
2020-04-27parse: refine error format reportingChih-Min Chao1-10/+24
2020-04-27rvv: commitlog: fix comparision dst informationChih-Min Chao3-6/+9
2020-04-24rvv: commitlog: fix missing informaiton for slide1Chih-Min Chao4-12/+12
2020-04-24rvv: commitlog: fix dst information for int comparisonChih-Min Chao1-20/+40
2020-04-23build: quota string with [] to avoid part of string missingChih-Min Chao1-1/+1
2020-04-23rvv: fix vfncvt.xu.f.w for fp16Chih-Min Chao1-1/+1
2020-04-23rvv: aad fp16 support for vfwxxx.[wv]vChih-Min Chao10-8/+47
2020-04-22rvv: fix segment load/store nf checkingChih-Min Chao2-9/+11
2020-04-21rvv: fix vfmv for fp16Chih-Min Chao3-13/+36
2020-04-21rvv: fix vfmerge.vfm for fp16Chih-Min Chao1-2/+15
2020-04-21rvv: fix vfslide for fp16Chih-Min Chao2-0/+16
2020-04-21rvv: fix floating comparison for fp16Chih-Min Chao10-11/+49
2020-04-21rvv: allow fp16Chih-Min Chao1-1/+2
2020-04-20rvv: refine vfncvt case for f32_to_[u]i16 casesChih-Min Chao3-6/+3
2020-04-20rvv: fix f16_to_[u]i16 conversionChih-Min Chao4-8/+4
2020-04-20rvv: remove debug messageChih-Min Chao1-1/+0
2020-04-19rvv: fix vfwredsum checking ruleChih-Min Chao1-1/+3
2020-04-16rvv: fix rtz cvtChih-Min Chao13-51/+47
2020-04-15rvv: add widen conversion instructionsChih-Min Chao7-51/+53
2020-04-15rvv: add narrow conversion instrucitonsChih-Min Chao7-42/+71
2020-04-15rvv: add normal and widen reduction instructionsChih-Min Chao7-27/+78
2020-04-15rvv: add vmfxx f16 compare instructionsChih-Min Chao11-2/+39
2020-04-15rvv: add .vf fp16 instructionsChih-Min Chao25-3/+85