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| author | Dave.Wen <dave.wen@sifive.com> | 2020-05-18 02:07:19 -0700 |
|---|---|---|
| committer | Dave.Wen <dave.wen@sifive.com> | 2020-05-18 02:07:19 -0700 |
| commit | 58232218158365f05dfb11ba3f6c8d80f0a7f30d (patch) | |
| tree | 4651f4a620ada5d936102221aeb618d1426b17ac /riscv | |
| parent | ab6fd59262bc8593bf4dd26175cbe0d818fbda17 (diff) | |
| download | spike-58232218158365f05dfb11ba3f6c8d80f0a7f30d.zip spike-58232218158365f05dfb11ba3f6c8d80f0a7f30d.tar.gz spike-58232218158365f05dfb11ba3f6c8d80f0a7f30d.tar.bz2 | |
rvv: vid's mlen overlap checking
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/insns/vid_v.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/vid_v.h b/riscv/insns/vid_v.h index 97a0049..dc9a2d1 100644 --- a/riscv/insns/vid_v.h +++ b/riscv/insns/vid_v.h @@ -7,7 +7,7 @@ reg_t rd_num = insn.rd(); reg_t rs1_num = insn.rs1(); reg_t rs2_num = insn.rs2(); require((rd_num & (P.VU.vlmul - 1)) == 0); -if (insn.v_vm() == 0 && P.VU.vlmul >= 2) \ +if (insn.v_vm() == 0) \ require(insn.rd() != 0); for (reg_t i = P.VU.vstart ; i < P.VU.vl; ++i) { |