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AgeCommit message (Expand)AuthorFilesLines
2020-09-22Separate build of spike and spike-dasmAndrew Waterman3-35/+4
2020-09-22Don't error out if dlopen isn't availableAndrew Waterman1-3/+1
2020-09-21Raise virtual-instruction traps correctly for WFI/SRET/SFENCEAndrew Waterman3-4/+6
2020-09-20Fix polarity of hstatus.HU fieldAndrew Waterman13-13/+13
2020-09-20Don't throw virtual instruction exceptions for unimplemented CSRsAndrew Waterman9-115/+133
2020-09-15rvv: fix int type is not enough to do shift (#544)Han-Kuan Chen2-2/+2
2020-09-15Populate tval registers on illegal-/virtual-instruction trapsAndrew Waterman9-20/+26
2020-09-15No need to catch illegal CSRs in set_csrAndrew Waterman1-16/+2
2020-09-11Add MIP_MEIP to all_ints (#543)Abhinay Kayastha1-1/+1
2020-09-01Fix MIDELEG and MEDELEG emulation when H-extension is available (#537)Anup Patel1-0/+7
2020-08-31rvv: reading vcsr needs to enable mstatus.vsChih-Min Chao1-0/+1
2020-08-31rvv: relax checking for vs1Chih-Min Chao3-2/+31
2020-08-31rvv: trigger exp for illegal ncvt/wcvt eewChih-Min Chao16-26/+26
2020-08-31rvv: check invalid frm for floating operationsChih-Min Chao3-0/+4
2020-08-31rvv: add reciprocal instructionsChih-Min Chao4-0/+30
2020-08-27rf: remove bit extraction from processor.hChih-Min Chao3-9/+18
2020-08-27rvv: remove quad instructionsChih-Min Chao11-60/+0
2020-08-20Fix debug tests failing with impebreak enabled. (#530)Tim Newsome1-1/+1
2020-08-20rvv: fix vrgatherei16 overlap ruleChih-Min Chao1-1/+2
2020-08-12mcounteren does not exist if U-mode is not implementedAndrew Waterman1-1/+4
2020-08-11Add option to dissable implicit ebreak in program bufferSamuel Obuch2-6/+10
2020-08-04Merge pull request #521 from chihminchao/op-hypvervisorAndrew Waterman3-51/+51
2020-08-03op: hyperviosr: fix exception code and nameChih-Min Chao3-6/+6
2020-08-03op: rearrange hypbervisor op/csr/causeChih-Min Chao1-46/+46
2020-08-03rvv: add 'vstartalu" option to --varch arugmentChih-Min Chao23-36/+45
2020-08-03op: rvv: fix pesudo code instructionsChih-Min Chao1-3/+3
2020-07-29f16: fix Nan-Box macroChih-Min Chao1-1/+1
2020-07-29rvv: fix frac_lmul get functionChih-Min Chao1-1/+1
2020-07-29rvv: remove isa string zvamoand zvlssegChih-Min Chao3-18/+0
2020-07-29rvv: remove veew/vemul stateChih-Min Chao3-32/+25
2020-07-29rvv: add vrgatherei16.vvChih-Min Chao3-0/+37
2020-07-29rvv: add new whole reg load/store instructionsChih-Min Chao24-21/+187
2020-07-29rvv: op: rearrange some instruction since generation order changeChih-Min Chao1-36/+36
2020-07-29rvv: op: fix amo namingChih-Min Chao38-144/+144
2020-07-29rvv: remove slenChih-Min Chao2-8/+5
2020-07-29rvv: initialize vector register as zeroChih-Min Chao1-1/+2
2020-07-28Incorporate RVV 1.0 vtype layout changeAndrew Waterman2-5/+4
2020-07-16Fix legalize_privilege for extension H (#508)Abhinay Kayastha1-1/+1
2020-07-15commitlog: fix vmvnfr.v register information (#506)Chih-Min Chao1-4/+17
2020-07-13rvv: fix viota.m dst and src overlapping rule (#504)Chih-Min Chao1-5/+1
2020-07-09Merge pull request #493 from avpatel/riscv-hyp-ext-v0.6.1Andrew Waterman34-145/+924
2020-07-09Add bootargs command-line option to SpikeAnup Patel4-7/+21
2020-07-09Implement new instructions of hypervisor extensionAnup Patel16-0/+81
2020-07-09Implement hypervisor two-stage MMUAnup Patel2-51/+179
2020-07-09Implement hypervisor CSRs read/writeAnup Patel8-53/+502
2020-07-08rvv: vstart register needs only lg2(VLEN) bits (#501)Chih-Min Chao1-1/+1
2020-07-08Extend trap classes to pass more informationAnup Patel7-28/+60
2020-07-08Add hypervisor extension related CSR and instruction definesAnup Patel1-6/+81
2020-07-06If n_pmp=0, then pmp is not implemented hence raise trapAbhinay Kayastha1-0/+3
2020-07-02commitlog: support csr accessChih-Min Chao2-2/+99
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