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| author | Anup Patel <anup.patel@wdc.com> | 2020-09-02 06:57:42 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-09-01 18:27:42 -0700 |
| commit | 3101b47288f3156d24b598449d4f8428875b7ed1 (patch) | |
| tree | cf994b7879fb260bf9fd3c9ca4e8399f8173e669 /riscv | |
| parent | f974ce1c6d30250d46d2b763715724bcd4b7a89d (diff) | |
| download | spike-3101b47288f3156d24b598449d4f8428875b7ed1.zip spike-3101b47288f3156d24b598449d4f8428875b7ed1.tar.gz spike-3101b47288f3156d24b598449d4f8428875b7ed1.tar.bz2 | |
Fix MIDELEG and MEDELEG emulation when H-extension is available (#537)
This patch does two fixes when H-extension is available:
1. The MEDELEG should allow delegating VIRTUAL_SUPERVISOR_ECALL instead
of SUPERVISOR_ECALL. This was broken after commit 7775c6fb7cc1b.
2. The forced bits in MIDELEG should be cleared when 'H' bit is
cleared in MISA CSR.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/processor.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 707aea6..37eb246 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -899,6 +899,7 @@ void processor_t::set_csr(int which, reg_t val) (1 << CAUSE_LOAD_PAGE_FAULT) | (1 << CAUSE_STORE_PAGE_FAULT); mask |= supports_extension('H') ? + (1 << CAUSE_VIRTUAL_SUPERVISOR_ECALL) | (1 << CAUSE_FETCH_GUEST_PAGE_FAULT) | (1 << CAUSE_LOAD_GUEST_PAGE_FAULT) | (1 << CAUSE_VIRTUAL_INSTRUCTION) | @@ -1040,6 +1041,12 @@ void processor_t::set_csr(int which, reg_t val) mask &= max_isa; state.misa = (val & mask) | (state.misa & ~mask); + + // update the forced bits in MIDELEG + if (supports_extension('H')) + state.mideleg |= MIDELEG_FORCED_MASK; + else + state.mideleg &= ~MIDELEG_FORCED_MASK; break; } case CSR_HSTATUS: { |